PI6LC48P02 2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator Features Description Two differential LVPECL output pairs e PTh I6LC48P02 is a 2-output LVPECL synthesizer optimized to generate Fibre Channel, Ethernet and storage reference clock Selectable crystal oscillator interface or LVCMOS/LVTTL frequencies and is a member of Pericoms HiFlex family of high single-ended clock input performance clock solutions. Using a 26.5625MHz crystal, the Supports the following output frequencies: most popular Fibre Channel (FC) frequencies can be generated Ethernet: 50MHz, 100MHz, 150MHz, 156.25MHz, based on the settings of 2 frequency select pins. Using 25MHz 200MHz Xtal, most Ethenrnet frequencies inckuding 100MHz can be generated, while using 26.041667MHz Xtal, 156.25MHz can be Fibre Channel: 53.125MHz, 106.25MHz, 159.375MHz, generated for Networking applications. 187.5MHz, 212.5MHz e PTh I6LC48P02 uses Pericoms proprietary low phase noise RMS phase jitter 212.5MHz, using a 26.5625MHz crystal PLL technology to achieve ultra low phase jitter, it is ideal for (12kHz 20MHz): 0.28ps (typical) Networking, data center, and storage systems. RMS phase jitter 100MHz, using a 25MHz crystal (12kHz 20MHz): 0.32ps (typical) RMS phase jitter 156.25MHz, using a 26.041667MHz Applications crystal (12kHz 20MHz): 0.30ps (typical) Networking and Data Center Server systems Full 3.3V or 2.5V supply modes Fibre Channel (FC) and Storage systems Industrial operating temperature Available in lead-free package: 20-TSSOP Block Diagram XTAL IN OSC PFD VCO XTAL OUT CLK0 /N CLK0 Ref IN CLK1 M CLK1 IN SEL PLL ByPass N SEL 0:1 M reset www.pericom.com PI6LC48P02 Rev. C 08/13/15 15-0102 1PI6LC48P02 2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator Pin Configuration NC 1 20 VDDO VDDO 2 19 CLK1 CLK0 3 18 CLK1 CLK0 4 17 GND M reset 16 VDD 5 PLL ByPass 6 15 IN SEL Ref IN NC 7 14 13 XTAL IN VDDA 8 12 XTAL OUT N SEL0 9 11 VDD 10 N SEL1 Pinout Table Pin No. Pin Name I/O Type Description 1, 7 NC No connection 2, 20 VDDO Power - Output Power Supply 3,4 CLK0, CLK0 Output - LVPECL Output clock 0 Master reset. 1, CLK0/CLK1 go to low, CLK0 /CLK1 go to 5 M reset Input Pull-down high 0 outputs are enabled 6 PLL ByPass Input Pull-down PLL bypass select. 0 PLL is enabled, 1 PLL is bypassed 8 VDDA Power - Analog Power Supply 9, 11 N SEL0, N SEL1 Input Pull-down Output frequency select 10, 16 VDD Power - Core Power Supply 12, 13 XOUT, XIN Crystal - Crystal input and output 14 Ref IN Input Pull-down CMOS reference clock input 15 IN SEL Input Pull-down 0 selects Crystal, 1 selects reference input 17 GND Ground - Ground CLK1 , 18, 19 Output - LVPECL Output clock 1 CLK1 www.pericom.com PI6LC48P02 Rev. C 08/13/15 15-0102 2