A product Line of Diodes Incorporated PI6CG18401 Very Low Power 4-Output PCIe Clock Generator With On-chip Termination Features Description 1.8V supply voltage e PTh I6CG18401 is an 4-output very low power PCIe Gen1/ Crystal/CMOS input: 25 MHz Gen2/Gen3/ Gen4 clock generator. It uses 25MHz crystal or 4 differential low power HCSL outputs with on-chip CMOS reference as an input to generate the 100MHz low power termination differential HCSL outputs with on-chip terminations. e oTh n-chip termination can save 16 external resistors and make Individual output enable layout easier. An additional buffered reference output is provid - Reference CMOS output ed to serve as a low noise reference for other circuitry. Programmable Slew rate and output amplitute for each output It uses Diodes proprietary PLL design to achieve very low jitter Differential outputs blocked until PLL is locked that meets PCIe Gen1/Gen2/Gen3 requirements. It also pro- vides various options such as different slew rate and amplitude Selectable 0%, -0.25% or -0.5% spread on differential outputs through strapping pins or SMBUS so that users can configure Strapping pins or SMBus for configuration the device easily to get the optimized performance for their 3.3V tolerant SMBus interface support individual boards. The device also supports selectable spread- Very low jitter outputs spectrum options to reduce EMI for various applications. Differential cycle-to-cycle jitter <50ps Differential output-to-output skew <50ps PCIe Gen1/Gen2/Gen3/ Gen4 compliant CMOS REFOUT phase jitter is < 1.5ps RMS Packaging (Pb-free & Green): 32-lead 55mm TQFN Pin Configuration 32 31 30 29 28 27 26 25 1 OE2 GND XTAL 24 Q2- XTAL IN/CLK 2 23 XTAL OUT 3 22 Q2+ V 4 21 VDDA DD OSC GND V 5 GNDA DD REFOUT 20 Q1- SADR/REFOUT 6 19 Q1+ GND REFOUT 7 18 GND DIG 8 OE1 17 9 10 11 12 13 14 15 16 www.diodes.com July 2017 PI6CG18401 1 Diodes Incorporated Document number DS39948 Rev D V DD DIG SS SEL TRI SCLK PD SDATA GND OE0 OE3 Q0+ Q3- Q0- Q3+ GND GND V DDO V DDOA product Line of Diodes Incorporated PI6CG18401 Block Diagram REFOUT OE 3:0 Q3 Q2 XTAL IN/CLK OSC PLL XTAL OUT SS Q1 SCLK Q0 SDATA SADR CTRL SS SEL TRI LOGIC PD Pin Description Pin Pin Name Type Description 1 GND XTAL Power Ground for oscillator circuit 2 XTAL IN/CLK Input Crystal input or CMOS reference input 3 XTAL OUT Output Crystal output 4 V OSC Power Power supply for oscillator circuitry, nominal 1.8V DD 5 V REFOUT Power Power supply for buffered CMOS output DD Input/ Latch to select SMBus Address or 1.8V LVCMOS REFOUT. This pin has 6 SADR/REFOUT CMOS Output internal pull-down. 7 GND REFOUT Power Ground for REFOUT 8 GND DIG Power Ground for digital circuitry 9 V DIG Power Power supply for digital circuitry, nominal 1.8V DD 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 11 SDATA CMOS SMBUS Data line, 3.3V tolerant Output Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15, 26, 30 GND Power Ground 16, 25 V Power Power supply for differential outputs DDO Active low input for enabling Q1 pair. This pin has an internal pull-down. 17 OE1 Input CMOS 1 =disable outputs, 0 = enable outputs 18 Q1+ Output HCSL Differential true clock output 19 Q1- Output HCSL Differential complementary clock output 20 GNDA Power Ground for analog circuitry www.diodes.com July 2017 PI6CG18401 22 Diodes Incorporated Document number DS39948 Rev D