ispClock 5600 Family In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer February 2005 Data Sheet Up to +/- 12ns skew range Features Coarse and ne adjustment modes 10MHz to 320MHz Input/Output Operation Up to Five Clock Frequency Domains Low Output to Output Skew (<50ps) Flexible Clock Reference and External Low Jitter Peak-to-Peak (<60ps) Feedback Inputs Up to 20 Programmable Fan-out Buffers Programmable input standards Programmable output standards and individual - LVTTL, LVCMOS, SSTL, HSTL, LVDS, enable controls LVPECL - LVTTL, LVCMOS, HSTL, SSTL, LVDS, Clock A/B selection multiplexer LVPECL Feedback A/B selection multiplexer Programmable output impedance Programmable termination - 40 to 70 in 5 increments Four User-programmable Proles Stored in Programmable slew rate 2 E CMOS Memory Up to 10 banks with individual V and GND CCO Supports both test and multiple operating - 1.5V, 1.8V, 2.5V, 3.3V congurations Fully Integrated High-Performance PLL Full JTAG Boundary Scan Test In-System Programmable lock detect Programming Support Multiply and divide ratio controlled by Exceptional Power Supply Noise Immunity - Input divider (5 bits) Commercial (0 to 70C) and Industrial - Feedback divider (5 bits) (-40 to 85C) Temperature Ranges - Five output dividers (5 bits) Programmable On-chip Loop Filter 100-pin and 48-pin TQFP Packages Applications Precision Programmable Phase Adjustment Circuit board common clock generation and (Skew) Per Output distribution 16 settings minimum step size 195ps PLL-based frequency generation - Locked to VCO frequency High fan-out clock buffer Zero-delay clock buffer Product Family Block Diagram LOCK DETECT OUTPUT DIVIDERS SKEW OUTPUT CONTROL DRIVERS V0 BYPASS MUX V1 M * V2 PHASE/ FREQUENCY FILTER VCO DETECTOR V3 N OUTPUT V4 ROUTING PLL CORE MATRIX Internal/External JTAG Feedback Multiple Profile INTERFACE Select Management Logic & 2 E CMOS 021 3 * MEMORY INTERNAL FEEDBACK PATH * Input Available only on ispClock5620 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 clk5600 02.1 FEEDBACK REFERENCE INPUTS INPUTS CLOCK OUTPUTS Lattice Semiconductor ispClock5600 Family Data Sheet General Description and Overview The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5610 provides up to 10 sin- gle-ended or ve differential clock outputs, while the ispClock5620 provides up to 20 single-ended or 10 differential clock outputs. Each pair of outputs may be independently congured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro- grammable control of termination, slew-rate, and timing skew. All conguration information is stored on-chip in non- 2 volatile E CMOS memory. The ispClock5600s PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of ve post-PLL V-divid- ers provides additional exibility by supporting the generation of ve separate output frequencies. Loop feedback may be taken internally from the output of any of the ve V-dividers, or externally through FBKA+/- or FBKB+/- pins. The core functions of all members of the ispClock5600 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ispClock5610 and ispClock5620. Table 1. ispClock5600 Family Members Device Ref. Input Pairs Feedback Input Pairs Clock Outputs ispClock5610 1 1 10 ispClock5620 2 2 20 Figure 1. ispClock5610 Functional Block Diagram PS0 PS1 LOCK RESET PLL BYPASS SGATE GOE OEX OEY Profile Select Control OUTPUT ENABLE CONTROLS 01 2 3 LOCK OUTPUT ROUTING SKEW OUTPUT DETECT MATRIX CONTROL DRIVERS OUTPUT BANK 0A DIVIDERS BANK 0B V0 (2-64) BANK 2A BANK 2B INPUT V1 (2-64) DIVIDER BANK 4A M REFA+ 1 BANK 4B V2 REFA- (1-32) PHASE LOOP (2-64) VCO 0 BANK 5A DETECT FILTER REFVTT BANK 5B V3 (2-64) BANK 7A FEEDBACK BANK 7B N V4 (1-32) DIVIDER (2-64) FEEDBACK 2 E Configuration SKEW ADJUST FBKA+ FBKA - FBKVTT JTAG INTERFACE TDI TMS TCK TDO 2