CM1236 ESD Clamp Array for High Speed Data Line Protection Product Description The CM1236 is ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading and tightly CM1236 Figure 1. Block Diagram ESD Protection Architecture characteristic impedance that helps optimize 100 load Conceptually, an ESD protection device performs the impedance applications such as the HDMI high speed data following actions upon an ESD strike discharge into a lines. protected ASIC (see Figure 2): NOTE: When each of the channels are used individually 1. When an ESD potential is applied to the system for singleended signal lines protection, the under test (contact or airdischarge), Kirchoffs individual channel provides 50 characteristic Current Law (KCL) dictates that the Electrical impedance matching. Overstress (EOS) currents will immediately divide The load impedance matching feature of the CM1236 throughout the circuit, based on the dynamic helps to simplify system designers PCB layout impedance of each path. considerations in impedance matching and also eliminates associated passive components. 2. Ideally, the classic shunt ESD clamp will switch The route through the architecture enables the CM1236 to within 1 ns to a lowimpedance path and return provide matched impedance for the signal path between the the majority of the EOS current to the chassis connector and the ASIC. Besides this function, this circuit shield/reference ground. In actuality, if the ESD arrangement also changes the way the parasitic inductance components response time (t ) is slower CLAMP interacts with the ESD protection circuit and helps reduce than the ASIC it is protecting, or if the Dynamic the I current to the ASIC. RESIDUAL Clamping Resistance (R ) is not significantly DYN lower than the ASICs I/O cell circuitry, then the ASIC will have to absorb a large amount of the EOS energy, and be more likely to fail. 3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, and be ready for an additional strike. Any deterioration in parasitics or clamping capability should be considered a failure, since it can then affect signal integrity or subsequent protection capability. (This is known as multistrike capability.) In the CM1236 architecture, the signal line leading the Figure 2. Standard ESD Protection Device Block connector to the ASIC routes through the CM1236 chip Diagram which provides 100 matched differential channel