MC10EP139, MC100EP139 3.3 V / 5 VECL 2/4, 4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The www.onsemi.com internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on 1 1 the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the TSSOP20 WB SOIC20 WB QFN20 falling edge of the input clock, therefore, all associated specification DT SUFFIX DW SUFFIX MN SUFFIX CASE 948E CASE 751D CASE 485E limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state therefore the master reset (MR) input may require assertion to ensure MARKING DIAGRAMS* system synchronization. Internal divider design ensures synchronization between the 2/4 and the 4/5/6 outputs within a device. All V and CC 20 20 V pins must be externally connected to power supply to guarantee EE 1 HEP or KEP XXXX MCXXXEP139 proper operation. EP139 139 AWLYYWWG The V Pin, an internally generated voltage supply, is available to this ALYW ALYW BB device only. For Single-Ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also BB BB 1 TSSOP20 WB SOIC20 WB QFN20 rebias AC coupled inputs. When used, decouple V and V via a BB CC 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When HEP = MC10EP not used, VBB should be left open. KEP = MC100EP The 100 Series contains temperature compensation. XXX = 10 or 100 A = Assembly Location L,WL = Wafer Lot Features Y, YY = Year Maximum Frequency = > 1.0 GHz Typical W, WW = Work Week 50 ps Output-to-Output Skew G or = Pb-Free Package (Note: Microdot may be in either location) PECL Mode Operating Range: V = 3.0 V to 5.5 V with V = 0 V *For additional marking information, refer to CC EE Application Note AND8002/D. NECL Mode Operating Range: V = 0 V with V = 3.0 V to 5.5 V CC EE Open Input Default State ORDERING INFORMATION Safety Clamp on Inputs See detailed ordering and shipping information in the package Synchronous Enable/Disable dimensions section on page 11 of this data sheet. Master Reset for Synchronization of Multiple Chips V Output BB These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 14 MC10EP139/DMC10EP139, MC100EP139 V Table 1. PIN DESCRIPTION 1 20 CC V CC PIN FUNCTION EN 2 19 Q0 CLK*, CLK* ECL Differential Clock Inputs DIVSELb0 3 18 Q0 EN* ECL Sync Enable CLK 4 17 Q1 MR* ECL Master Reset CLK 5 16 Q1 MC10/100EP139 V ECL Reference Output BB V BB 6 15 Q2 Q0, Q1, Q0, Q1 ECL Differential 2/4 Outputs MR 14 7 Q2 Q2, Q3, Q2, Q3 ECL Differential 4/5/6 Outputs V CC Q3 8 13 DIVSELa* ECL Frequency Select Input 2/4 DIVSELb1 9 12 Q3 DIVSELb0* ECL Frequency Select Input 4/5/6 V DIVSELa EE 11 10 DIVSELb1* ECL Frequency Select Input 4/5/6 V ECL Positive Supply CC Warning: All V and V pins must be externally connected to CC EE a Power Supply to guarantee proper operation. V ECL Negative Supply EE Figure 1. 20-Lead Pinout (Top View) EP Exposed Pad *Pins will default low when left open. Exposed Pad 20 19 18 17 16 1 15 DIVSELb0 Q1 2 14 CLK Q1 MC10/100EP139 3 13 CLK Q2 4 V 12 Q2 BB 5 11 MR Q3 67 8 9 10 Warning: All V and V pins must be externally connected to a Power Supply to CC EE guarantee proper operation. The Exposed Pad (EP) on package bottom must be attached to a heat-sinking con- duit. The Exposed Pad may only be electrically connected to V . EE Figure 2. QFN-20 Pinout (Top View) www.onsemi.com 2 V EN CC DIVSELb1 V CC V DIVSELa CC V Q0 EE Q0 Q3