3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator NB100ELT23L Description www.onsemi.com The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used, MARKING only +3.3 V and ground are required. The small outline 8-lead package DIAGRAMS* and the dual gate design of the ELT23L makes it ideal for applications which require the translation of a clock and a data signal. 8 The ELT23L is available in only the ECL 100K standard. Since SOIC8 KT23L there are no LVPECL outputs or an external V reference, the D SUFFIX ALYW BB 8 CASE 751 ELT23L does not require both ECL standard versions. The LVPECL 1 1 inputs are differential. Therefore, the NB100ELT23L can accept any standard differential LVPECL/LVDS input referenced from a V of CC +3.3 V. 8 TSSOP8 Features K23L 8 DT SUFFIX ALYW 2.1 ns Typical Propagation Delay CASE 948R 1 Maximum Operating Frequency > 160 MHz 1 24 mA LVTTL Outputs A = Assembly Location Operating Range: V = 3.0 V to 3.6 V with GND = 0 V CC L = Wafer Lot Y = Year These Devices are PbFree, Halogen Free/BFR Free and are RoHS W = Work Week Compliant = PbFree Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping 2500 / Tape & SOIC8 NB100ELT23LDR2G Reel (PbFree) TSSOP8 100 Units / NB100ELT23LDTG (PbFree) Tube TSSOP8 2500 / Tape & NB100ELT23LDTR2G (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2021 Rev. 13 NB100ELT23L/DNB100ELT23L Table 1. PIN DESCRIPTION D0 1 8 V CC PIN FUNCTION Q0, Q1 LVTTL Outputs D0*, D1* Differential LVPECL Inputs D0 2 7 Q0 D0**, D1** LVPECL LVTTL V Positive Supply CC GND Ground D1 3 6 Q1 *Pins will default to V /2 when left open. If connected to a CC common termination voltage under no signal conditions, then the device will be susceptible to selfoscillation. **Pins will default to 2/3 V when left open. If connected to a D145 CC GND common termination voltage under no signal conditions, then the device will be susceptible to self oscillation. See AND8020, Section 6 for options. Figure 1. 8Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor D 50 k D 75 k Internal Input Pullup Resistor 50 k ESD Protection Human Body Model > 1.5 kV Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PbFree Pkg SOIC8 Level 1 TSSOP8 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 1.25 in Transistor Count 91 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2