Product Information

NB3N51032DTR2G

NB3N51032DTR2G electronic component of ON Semiconductor

Datasheet
Clock Generator 25MHz Input 200MHz Output 16-Pin TSSOP T/R

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2500: USD 2.3603 ea
Line Total: USD 5900.75

0 - Global Stock
MOQ: 2500  Multiples: 2500
Pack Size: 2500
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2500
Multiples : 2500

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NB3N51032DTR2G
ON Semiconductor

2500 : USD 2.3603

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2500
Multiples : 2500

Stock Image

NB3N51032DTR2G
ON Semiconductor

2500 : USD 3.0972

     
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NB3N51032 3.3 V, Crystal to 25 MHz, 100 MHz, 125 MHz and 200 MHz Dual HCSL/LVDS Clock Generator The NB3N51032 is a precision, low phase noise clock generator that www.onsemi.com supports PCI Express and Ethernet requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal and generates a MARKING differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz DIAGRAM clock frequencies. Outputs can interface with LVDS with proper 16 16 termination (See Figure 10). The NB3N51032 provides selectable NB3N spread options of 0.5% and 0.75% for applications demanding low 1032 1 ALYW TSSOP16 Electromagnetic Interference (EMI) as well as optimum performance DT SUFFIX 1 with no spread option. CASE 948F Features A = Assembly Location Uses 25 MHz Fundamental Mode Parallel Resonant Crystal L = Wafer Lot Y = Year External Loop Filter is Not Required W = Work Week HCSL Differential Output or LVDS with Proper Termination = PbFree Package (Note: Microdot may be in either location) Four Selectable Multipliers of the Input Frequency Output Enable with TriState Outputs ORDERING INFORMATION PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant See detailed ordering and shipping information on page 11 of this data sheet. Spread of 0.5%, 0.75% and No Spread Applications Phase Noise: 100 MHz Networking Offset Noise Power 100 Hz 88 dBc/Hz Consumer 1 kHz 118 dBc/Hz Computing and Peripherals 10 kHz 131 dBc/Hz Industrial Equipment 100 kHz 132 dBc/Hz PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4 1 MHz 144 dBc/Hz Gigabit Ethernet 10 MHz 155 dBc/Hz FB DIMM Typical Period Jitter RMS of 1.5 ps Operating Supply Voltage Range 3.3 V 5% End Products Industrial Temperature Range 40C to +85C Switch and Router Functionally Compatible with IDT55703, Set Top Box, LCD TV IDT5V41065, IDT5V41235 with enhanced performance Servers, Desktop Computers These are PbFree Devices Automated Test Equipment V SS0 SS1 DD Spread Spectrum Circuit X1/CLK Clock Buffer Phase Charge CLK0 VCO HCSL 25 MHz Clock or Crystal Oscillator Pump Detector Output CLK0 Crystal X2 CLK1 HCSL N CLK1 Output V = VDDODA = VDDXD DD GND S0 S1 OE IREF GND = GNDODA = GNDXD Figure 1. NB3N51032 Simplified Logic Diagram Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: September, 2017 Rev. 3 NB3N51032/DNB3N51032 S0 1 16 VDDXD S1 2 15 CLK0 SS0 3 14 CLK0 X1/CLK 4 13 GNDODA X2 5 12 VDDODA OE 6 11 CLK1 GNDXD 7 10 CLK1 SS1 8 9 IREF Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output 1 S0 Input select table 2 for details. LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output 2 S1 Input select Table 2 for details. LVTTL/LVCMOS Spread select input 0. Internal pullup resistor to VDDXD. See Spread se- 3 SS0 Input lection Table 3 for details. 4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or singleended clock. 5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input. 6 OE Input Output enable tristates output when connected to GND. Internal pullup resistor to VDDXD. 7 GNDXD Power Supply Ground 0 V. This pin provides GND return path for the device. LVTTL/LVCMOS Spread select input 1. Internal pullup resistor to VDDXD. See Spread se- 8 SS1 Input lection Table 3 for details. Output current reference pin. Precision resistor (typ. 475 ) is connected to set the output 9 IREF Output current. HCSL or 10 CLK1 Inverted clock output. (For LVDS levels see Figure 10) LVDS Output HCSL or 11 CLK1 Noninverted clock output. (For LVDS levels see Figure 10) LVDS Output 12 VDDODA Power Supply Positive supply voltage pin connected to +3.3 V supply voltage. 13 GNDODA Power Supply Ground 0 V. These pins provide GND return path for the devices. HCSL or 14 CLK0 Inverted clock output. (For LVDS levels see Figure 10) LVDS Output HCSL or 15 CLK0 Noninverted clock output. (For LVDS levels see Figure 10) LVDS Output 16 VDDXD Power Supply Positive supply voltage pin connected to +3.3 V supply voltage. www.onsemi.com 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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