TinyLogic UHS Dual 2-Input Exclusive-OR Gate NC7WZ86 Description The NC7WZ86 is a dual 2 Input Exclusive OR Gate from ONSemicoductors Ultra High Speed Series of TinyLogic. The www.onsemi.com device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power MARKING dissipation over a very broad V operating range. The device is CC DIAGRAMS specified to operate over the 1.65 V to 5.5 V V range. The inputs CC and output are high impedance when V is 0 V. Inputs tolerate CC UQFN8 N7KK voltages up to 5.5 V independent of V operating voltage. CC 1.6X1.6, 0.5P XYZ CASE 523AY Features Space Saving US8 Surface Mount Package MicroPak PbFree Leadless Package Ultra High Speed: t 2.9 ns Typ. into 50 pF at 5 V V PD CC WZ86 High Output Drive: 24 mA at 3 V V US8 CC ALYW CASE 846AN Broad V Operating Range: 1.65 V to 5.5 V CC Matches the Performance of LCX when Operated at 3.3 V V CC Power Down High Impedance Inputs / Output Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation N7, WZ86 = Specific Device Code Patented Noise / EMI Reduction Circuitry Implemented KK = 2Digit Lot Run Traceability Code XY = 2Digit Date Code Format These Devices are PbFree, Halogen Free/BFR Free and are RoHS Z = Assembly Plant Code Compliant A = Assembly Site L = Wafer Lot Number YW = Assembly Start Week IEEE/IEC ORDERING INFORMATION A = 1 1 Y See detailed ordering, marking and shipping information in the 1 B 1 package dimensions section on page 6 of this data sheet. A = 1 2 Y 2 B 2 Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: October, 2020 Rev. 2 NC7WZ86/DNC7WZ86 Connection Diagrams A B Y 1 1 2 7 6 5 A 1 8 V 1 CC B 2 7 Y 1 1 V 8 4 GND CC Y 3 6 B 2 2 GND45 A 1 2 3 2 Y B A 1 2 2 Figure 2. Connection Diagram Figure 4. Pad Assignments for MicroPak (Top View) (Top Thru View) (Top View) AAA Pin One AAA represents Product Code Top Mark see ordering code NOTE: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin One Orientation Diagram PIN DESCRIPTIONS FUNCTION TABLE (Y = A B) Pin Names Description Inputs Output A , B Input A B Y n n Y Output L L L n L H H H L H H H L H = HIGH Logic Level L = LOW Logic Level www.onsemi.com 2