Product Specification
PE43602
50 RF Digital Attenuator
6-bit, 31.5 dB, 9 kHz - 5.0 GHz
Product Description
Features
The PE43602 is a HaRP-enhanced, high linearity, 6-bit
RF Digital Step Attenuator (DSA) covering a 31.5 dB
HaRP-enhanced UltraCMOS device
attenuation range in 0.5 dB steps. This Peregrine 50 RF
Attenuation: 0.5 dB steps to 31.5 dB
DSA provides both a serial and parallel CMOS control
interface. It maintains high attenuation accuracy over
High Linearity: Typical +58 dBm IIP3
frequency and temperature and exhibits very low insertion
Excellent low-frequency performance
loss and low power consumption. Performance does not
3.3 V or 5.0 V Power Supply Voltage
change with V due to on-board regulator. This next
DD
generation Peregrine DSA is available in a 4x4 mm 24
Fast switch settling time
lead QFN footprint.
Programming Modes:
The PE43602 is manufactured on Peregrines Direct Parallel
UltraCMOS process, a patented variation of silicon-on-
Latched Parallel
insulator (SOI) technology on a sapphire substrate,
Serial
offering the performance of GaAs with the economy and
High-attenuation state @ power-up (PUP)
integration of conventional CMOS.
CMOS Compatible
No DC blocking capacitors required
Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
24-lead 4x4x0.85 mm QFN
Document No. 70-0248-06 www.psemi.com 2010 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE43602
Product Specification
Table 1. Electrical Specifications @ +25C, V = 3.3 V or 5.0 V
DD
Parameter Test Conditions Frequency Min Typical Max Units
Frequency Range 9 kHz 5 GHz
Attenuation Range 0.5 dB Step 0 31.5 dB
Insertion Loss 9 kHz 5 GHz 2.2 2.7 dB
0 dB - 31.5 dB Attenuation settings 9 kHz < 4 GHz (0.3 + 3)% dB
Attenuation Error 0 dB - 31.5 dB Attenuation settings 4 GHz 5 GHz +0.4 + 5% dB
0 dB - 31.5 dB Attenuation settings 4 GHz 5 GHz -0.3 - 3% dB
Return Loss 9 kHz - 5 GHz 18 dB
Relative Phase All States 9 kHz - 5 GHz 55 deg
P1dB (note 1) Input 20 MHz - 5 GHz 30 32 dBm
IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 5 GHz 58 dBm
Typical Spurious Value 1 MHz -110 dBm
Video Feed Through 10 mVpp
Switching Time 50% DC CTRL to 10% / 90% RF 650 ns
RF Trise/Tfall 10% / 90% RF 400 ns
RF settled to within 0.05 dB of final value
Settling Time 4 s
RBW = 5 MHz, Averaging ON
Note 1. Please note Maximum Operating Pin (50 ) of +23 dBm as shown in Table 3
Performance Plots
Figure 3. 0.5 dB Step Error vs. Frequency * Figure 4. 1 dB Attenuation vs. Attenuation State
200MHz 900MHz 1800MHz 2200MHz
PE43602 Attenuation
3000MHz 4000MHz 5000MHz
1
35
30
900 MHz
1800 MHz
2200 MHz
25
3800 MHz
0.5
5000 MHz
20
15
0
10
5
0
-0.5
0 4 8 121620242832
035 1015 20 25305
Attenuation Setting (dB)
Attenuation State
* Monotonicity is held so long as Step-Error does not cross below -0.5
Figure 5. 0.5 dB Major State Bit Error Figure 6. 0.5 dB Attenuation Error vs. Frequency
0.5dB State 1dB State 2dB State 4dB State
200MHz 900MHz 1800MHz 2200MHz
8dB State 16dB State 31.5dB State
3000MHz 4000MHz 5000MHz
2
2
1.5
1.5
1
1
0.5
0.5
0 0
-0.5 -0.5
-1 -1
-1.5 -1.5
-2 -2
0 4 8 121620 242832
0 1000 2000 3000 4000 5000
Frequency (MHz) Attenuation Setting (dB)
2010 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0248-06 UltraCMOS RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: