IDT2308A 3.3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK IDT2308A MULTIPLIER FEATURES: DESCRIPTION: Phase-Lock Loop Clock Distribution for Applications ranging The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is from 10MHz to 133MHz operating frequency designed to address high-speed clock distribution and multiplication applica- Distributes one clock input to two banks of four outputs tions. The zero delay is achieved by aligning the phase between the incoming Separate output enable for each output bank clock and the output clock, operable within the range of 10 to 133MHz. External feedback (FBK) pin is used to synchronize the outputs The IDT2308A has two banks of four outputs each that are controlled via two to the clock input select addresses. By proper selection of input addresses, both banks can be Output Skew <200 ps put in tri-state mode. In test mode, the PLL is turned off, and the input clock Low jitter <200 ps cycle-to-cycle directly drives the outputs for system testing purposes. In the absence of an 1x, 2x, 4x output options (see table): input clock, the IDT2308A enters power down. In this mode, the device will IDT2308A-1 1x draw less than 12A for Commercial Temperature range and less than 25A IDT2308A-2 1x, 2x for Industrial temperature range, and the outputs are tri-stated. IDT2308A-3 2x, 4x The IDT2308A is available in six unique configurations for both pre- IDT2308A-4 2x scaling and multiplication of the Input REF Clock. (See available options IDT2308A-1H and -2H for High Drive table.) No external RC network required The PLL is closed externally to provide more flexibility by allowing the user Operates at 3.3V VDD to control the delay between the input clock and the outputs. Available in SOIC and TSSOP packages The IDT2308A is characterized for both Industrial and Commercial opera- tion. FUNCTIONAL BLOCK DIAGRAM (-3, -4) 16 FBK 2 2 CLKA1 PLL 1 REF 3 CLKA2 14 CLKA3 15 CLKA4 8 S2 Control 9 Logic S1 2 (-2, -3) 6 CLKB1 7 CLKB2 10 CLKB3 11 CLKB4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AUGUST 2012 1 c 2012 Integrated Device Technology, Inc. DSC 6587/9IDT2308A 3.3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating Max. Unit VDD Supply Voltage Range 0.5 to +4.6 V (2) VI Input Voltage Range (REF) 0.5 to +5.5 V 1 16 REF FBK VI Input Voltage Range 0.5 to V 2 15 CLKA1 CLKA4 (except REF) VDD+0.5 3 14 IIK (VI < 0) Input Clamp Current 50 mA CLKA2 CLKA3 IO Continuous Output Current 50 mA 4 13 VDD VDD (VO = 0 to VDD) 5 12 GND GND VDD or GND Continuous Current 100 mA 6 TA = 55C Maximum Power Dissipation 0.7 W CLKB1 CLKB4 11 (3) (in still air) 7 CLKB2 10 CLKB3 TSTG Storage Temperature Range 65 to +150 C 8 9 Operating Commercial Temperature 0 to +70 C S2 S1 Temperature Range Operating Industrial Temperature -40 to +85 C Temperature Range SOIC/ TSSOP TOP VIEW NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. PIN DESCRIPTION 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. Pin Number Functional Description REF 1 Input Reference Clock, 5 Volt Tolerant Input (1) CLKA1 2 Clock Output for Bank A (1) CLKA2 3 Clock Output for Bank A VDD 4 3.3V Supply GND 5 Ground (1) CLKB1 6 Clock Output for Bank B APPLICATIONS: (1) CLKB2 7 Clock Output for Bank B SDRAM (2) S2 8 Select Input, Bit 2 Telecom (2) Datacom S1 9 Select Input, Bit 1 PC Motherboards/Workstations (1) CLKB3 10 Clock Output for Bank B Critical Path Delay Designs (1) CLKB4 11 Clock Output for Bank B GND 12 Ground VDD 13 3.3V Supply (1) CLKA3 14 Clock Output for Bank A (1) CLKA4 15 Clock Output for Bank A FBK 16 PLL Feedback Input NOTES: 1. Weak pull down on all outputs. 2. Weak pull ups on these inputs. 2