DATASHEET PECL INPUT OSCAR USER CONFIGURABLE CLOCK ICS525-03 Description Features The ICS525-03 are the most flexible way to generate a Packaged as 28-pin SSOP (150 mil body) high-quality, high-accuracy, high-frequency clock Highly accurate frequency generation output from a PECL input. The name OSCaR stands User determines the output frequency by setting all for OSCillator Replacement, as they are designed to internal dividers replace crystal oscillators in almost any electronic Eliminates need for custom oscillators system. The user can configure the device to produce No software needed nearly any output frequency from any input frequency Pull-ups on all select inputs by grounding or floating the select pins. Neither PECL input clock frequency of 0.5 to 250 MHz microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Output clock frequencies up to 250 MHz Loop (PLL) techniques, the device accepts a PECL Very low jitter clock to produce output clocks up to 250 MHz, keeping Operating voltage of 3.0 V or 5.5 V them frequency locked together. Resistors are for 25 mA drive capability at TTL levels PECL outputs only. Ideal for oscillator replacement For simple multipliers to produce common frequencies, Industrial temperature TM refer to the LOCO family of parts, which are smaller Pb (lead) free package and more cost effective. Advanced, low-power CMOS process This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. Block Diagram VDD 2 VDD 62 Ohm CLK1 Phase Comparator, 270 Ohm Reference Output PECLIN Charge Pump, and VCO Divider Divider PECLIN Loop Filter VDD VCO Divider 62 Ohm CLK2 270 Ohm 732 9 R6:R0 GND V8:V0 S2:S0 RES IDT PECL INPUT OSCAR USER CONFIGURABLE CLOCK 1 ICS525-03 REV L 010311ICS525-03 PECL INPUT OSCAR USER CONFIGURABLE CLOCK PECL MULTIPLIER RES Value Table Pin Assignment RES CLK1 CLK2 Pre-divide (P) R5 1 28 R4 R6 2 27 R3 0 CMOS CMOS 2 S0 3 26 R2 1.1 k Resistor PECL PECL 1 S1 4 25 R1 to VDD S2 5 24 R0 VDD 6 23 VDD PECL 7 22 CLK2 PECLIN 8 21 CLK1 GND 9 20 GND 10 19 V0 RES V1 11 18 V8 V2 12 17 V7 V3 13 16 V6 V4 14 15 V5 28-pin SSOP Output Divider and Maximum Output Frequency Table S2 S1 S0 CLK Max. Output Frequency (MHz) pin 5 pin 4 pin 3 Output Divider VDD = 5 V VDD = 3.3 V (OD) RES = 0 RES = 1.1 k RES = 0 RES = 1.1 k 0 0 0 6 67 34 40 20 0 0 1 2 200 100 120 60 0 1 0 8 50 25 30 15 0 1 1 4 100 50 60 30 1 0 0 5 80 40 48 24 1 0 1 7 57 29 34 17 1 1 0 1 250 200 200 125 1 1 1 3 133 80 80 40 Note: 0 = connect directly to ground 1 = connect directly to VDD. IDT PECL INPUT OSCAR USER CONFIGURABLE CLOCK 2 ICS525-03 REV L 010311