5P49EE602NLGI8 Renesas

DATASHEET VERSACLOCK LOW POWER CLOCK GENERATOR IDT5P49EE602 Description Features The IDT5P49EE602 is a programmable clock generator Four internal PLLs intended for low power, battery operated consumer Internal non-volatile EEPROM applications.There are four internal PLLs, each individually 2 Internal I C EEPROM master interface programmable, allowing for up to six differrent output 2 frequencies. The frequencies are generated from a single FAST (400kHz) mode I C serial interfaces reference clock. The reference clock can come from either Input Frequencies a TCXO or fundamental mode crystal. An additional TCXO: 10 MHz to 40 MHz 32.768kHz crystal oscillator is available to provide a real Crystal: 8 MHz to 30 MHz time clock or non-critical performance MHz processor RTC Crystal: 32.768 kHz clock. Output Frequency Ranges: kHz to 120 MHz The IDT5P49EE602 can be programmed through the use Each PLL has an 8-bit reference divider and a 11-bit 2 of the I C interfaces. The programming interface enables feedback-divider the device to be programmed when it is in normal operation 8-bit output-divider blocks or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore One of the PLLs support Spread Spectrum generation the configuration of the device without having to reprogram capable of configuration to pixel rate, with adjustable it on power-up. modulation rate and amplitude to support video clock with no visible artifacts Each of the four PLLs has an 8-bit reference divider and a 11-bit feedback divider. This allows the user to generate I/O Standards: four unique non-integer-related frequencies. The PLL loop Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS bandwidth is programmable to allow the user to tailor the 3 independent adjustable VDDO groups. PLL response to the application. For instance, the user can Programmable Slew Rate Control tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Programmable Loop Bandwidth Settings Spread spectrum generation is supported on one of the Programmable output inversion to reduce bimodal jitter PLLs. The device is specifically designed to work with Individual output enable/disable display applications to ensure that the spread profile Power-down/Sleep mode remains consistent for each HSYNC in order to reduce 10A max in power down mode ROW noise. It also may operate in standard spread 32kHz clock output active sleep mode sepctrum mode. 100 A max in sleep mode There are total five 8-bit output dividers. The outputs are 1.8V VDD Core Voltage connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any Available in 24pin 4x4mm QFN packages output bank. This feature can be used to simplify and -40 to +85 C Industrial Temp operation optimize the board layout. In addition, each output s slew rate and enable/disable function can be programmed. Target Applications Smart Mobile Handset Personal Navigation Device (PND) Camcorder DSC Portable Game Console Personal Media Player IDT VERSACLOCK LOW POWER CLOCK GENERATOR 1 IDT5P49EE602 REV L 111814IDT5P49EE602 VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Functional Block Diagram VDD VDDO1 VDDO2 VDDO3 XIN/REF REFSELA S XOUT PLLA R /DIV0 OUT0 C 0 REFSELB S R OUT1 /DIV1 PLLB(SS) C 1 SDA REFSELC Control S Logic /DIV2 OUT2 SCL PLLC R C 2 SEL 1:0 S /DIV3 OUT3 R REFSELD C 3 PLLD S OUT4A R /DIV4 C OUT4B 4 32kXIN 32kXOUT GND IDT VERSACLOCK LOW POWER CLOCK GENERATOR 2 IDT5P49EE602 REV L 111814