Programmable Clock Generator 5P49V5935 DATASHEET Description Features The 5P49V5935 is a programmable clock generator intended Generates up to four independent output frequencies for high-performance consumer, networking, industrial, High-performance, low phase noise PLL, < 0.7 ps RMS computing, and data-communications applications. typical phase jitter on outputs: Configurations may be stored in on-chip One-Time 2 PCIe Gen1, 2, 3 compliant clock capability Programmable (OTP) memory or changed using I C USB 3.0 compliant clock capability interface. This is IDTs fifth generation of programmable clock technology (VersaClock 5). 1GbE and 10GbE The 5P49V5935 by default uses an integrated 25MHz crystal Four fractional output dividers (FODs) as input reference. It also has a redundant external clock Independent spread spectrum capability on each output input. A glitchless manual switchover functions allows pair selection of either one as mentioned above as input reference Four banks of internal non-volatile in-system during normal operation. programmable or factory programmable OTP memory Two select pins allow up to 4 different configurations to be 2 I C serial programming interface programmed and accessible using processor GPIOs or One reference LVCMOS output clock bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial Four universal output pairs: power-down), regional standards (US, Japan, Europe) or Each configurable as one differential output pair or two system production margin testing. LVCMOS outputs 2 The device may be configured to use one of two I C I/O standards: addresses to allow multiple devices to be used in a system. Single-ended I/Os: 1.8V to 3.3V LVCMOS Differential I/Os: LVPECL, LVDS and HCSL Pin Assignment Input frequency ranges: LVDS, LVPECL, HCSL differential clock input (CLKIN, CLKINB) 1MHz to 350MHz Output frequency ranges: LVCMOS clock outputs: 1MHz to 200MHz LVDS, LVPECL, HCSL differential clock outputs: 1MHz to 350MHz Individually selectable output voltage (1.8V, 2.5V, 3.3V) for 24 23 22 21 20 19 1 V 2 18 DDO each output pair CLKIN 2 17 OUT2 CLKINB Redundant clock inputs with manual switchover NC 3 16 OUT2B Programmable loop bandwidth EPAD 4 V 3 NC 15 DDO Programmable output to output skew 5 14 V OUT3 DDA Programmable slew rate control 6 13 OUT3B CLKSEL Individual output enable/disable 8 7 910 11 12 Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA 4 x 4 mm 24-LGA package -40 to +85C industrial temperature operation 4 4 mm 24-LGA 5P49V5935 NOVEMBER 1, 2017 1 2017 Integrated Device Technology, Inc. SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V 1 V 4 DDO DDO OUT1 OUT4 OUT1B OUT4B5P49V5935 DATASHEET Functional Block Diagram V 0 DDO OSC OUT0 SEL I2CB 25MHz V 1 DDO OUT1 FOD1 OUT1B CLKIN V 2 DDO CLKINB OUT2 FOD2 OUT2B CLKSEL PLL V 3 DDO SD/OE OUT3 FOD3 OUT3B SEL1/SDA V 4 DDO OTP SEL0/SCL and OUT4 Control Logic FOD4 OUT4B V DDA V DDD Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1GbE and 10GbE PROGRAMMABLE CLOCK GENERATOR 2 NOVEMBER 1, 2017