650R-14ILF

DATASHEET NETWORKING SYSTEM CLOCK ICS650-14 Description Features The ICS650-14 is a low-cost, low-jitter, high-performance Packaged in 20-pin (150 mil) SSOP (QSOP) clock synthesizer customized for networking systems 25 MHz fundamental crystal clock or clock input applications. Using analog/digital Phase-Locked Loop (PLL) One fixed output clock of 25 MHz techniques, the device accepts a 25 MHz clock or fundamental mode crystal input to produce multiple output One bank of four frequency selectable output clocks clocks of one fixed 25 MHz, a four (plus one) frequency Three frequency selectable clocks outputs selectable bank, and two frequency selectable clocks. All Zero ppm synthesis error in all clocks output clocks are frequency locked together. All of the ICS650-14 outputs have zero ppm synthesis error. Ideal for networking systems Full CMOS output swing Advanced, low-power sub-micron CMOS process Operating voltage of 3.3 V or 5 V Industrial temperature range available Pb-free, RoHS compliant package Block Diagram VDD 2 2 4 SELA 0:1 CLKA 1:4 2 SELB 0:1 Clock CLKA5 Synthesis and SELC Control Circuitry CLKB CLKC X1/ICLK Crystal Buffer/ 25 MHz 25 MHz Crystal Crystal or Clock Oscillator X2 2 OE (all outputs) Optional crystal capacitors are shown and may be GND required for tuning of initial accuracy (determined once per board) IDT / ICS NETWORKING SYSTEM CLOCK 1 ICS650-14 REV H 051310ICS650-14 NETWORKING SYSTEM CLOCK CLOCKSYNTHESIZER Table 1 Pin Assignment 1 20 SELC SELA1 SELA0 CLKA1:4 CLKA5 SELB0 X2 2 19 SELA0 0 0 33.33 66.66 3 18 CLKA2 X1/ICLK 0M 50 75 VDD 4 17 CLKA3 0 1 66.67 133.33 SELB1 5 16 VDD M 0 100 33.33 GND 6 15 SELA1 M M 33.33 83.33 CLKB 7 14 GND M 1 50 125 CLKC 8 13 CLKA4 10 33.33 100 CLKA5 9 12 CLKA1 25M 10 11 OE 1M 25 75 11 66.67 100 20-pin (150 mil) SSOP Table 3 Table 2 SELC CLKC SELB1 SELB0 CLKB 0 CLKB/4 00 30 M 62.5 0M 27 1125 01 48 10 83.33 0 = connect directly to ground 1M 19.44 11 80 1 = connect directly to VDD M = leave unconnected (floating) Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 SELB0 TI Select pin for CLKB. See table 2. 2 X2 XO Crystal connection. Connect to a 25 MHz crystal or leave unconnected for clock input. 3 X1/ICLK XI Crystal connection. Connect to a 25 MHz fundamental crystal or clock input. 4 VDD P Connect to 3.3 V or 5 V. Must be same as other VDDs. 5 SELB1 I(Pu) Select pin for CLK B. See table 2. 6 GND P Connect to ground. 7 CLKB O Selectable clock output. See table 2. 8 CLKC O Selectable clock output. See table 3. 9 CLKA5 O Selectable clock output. See table 1. 10 25M Ou 25 MHz clock output. 11 OE I(Pu) Output enable. Tri-states all outputs when low. Internal pull-up. 12 CLKA1 O Selectable clock output. See table 1. IDT / ICS NETWORKING SYSTEM CLOCK 2 ICS650-14 REV H 051310