Low Skew, 1-TO-16 LVCMOS / LVTTL 8343-01 Fanout Buffer DATA SHEET General Description Features The 8343-01 is a low skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer. 16 LVCMOS/LVTTL outputs The 8343-01 single ended clock input accepts LVCMOS or LVTTL One LVCMOS/LVTTL clock input input levels. The ICS8343-01 operates at 3.3V, 2.5V and mixed 3.3V input and 2.5V supply modes over the commercial temperature CLK can accept the following input levels: LVCMOS, LVTTL range. Guaranteed output and part-to-part skew characteristics Maximum output frequency: 200MHz make the 8343-01 ideal for those clock distribution applications demanding well defined performance and repeatability. Dual output enable inputs facilitates 1-to-16 or 1-to-8 input to output modes All inputs are 5V tolerant Output skew: 250ps (maximum) Part-to-part skew: 700ps (maximum) Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply 0C to 70C ambient operating temperature Lead-Free packaging Industrial temperature information available upon request Block Diagram Pin Assignment VDD1 VDD VDD2 V V V DD1 DD DD2 CLK CLK Q0 Q15Q15 Q0 Q14Q14 Q1Q1 Q2Q2 Q13Q13 Q3 Q12Q12 Q3 Q11 Q4Q4 Q11 Q5 Q10 Q5 Q10 Q9 Q6 Q9 Q6 Q7 Q8Q8 Q7 OE1 GND OE2 OE1 GND OE2 32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package (Top View) 8343-01 REVISION B 08/25/14 1 2014 Integrated Device Technology, Inc.8343-01 DATA SHEET Pin Descriptions and Characteristics 1 Table 1. Pin Descriptions Number Name Type Description 1 V Power Q0 through Q7 output supply pin. DD1 2 V Power Q0 through Q7 output supply pin. DD1 3 V Power Q0 through Q7 output supply pin. DD1 4 Q3 Output LVCMOS/LVTTL clock output. 7typical output impedance. 5 Q4 Output LVCMOS/LVTTL clock output. 7typical output impedance. 6 GND Power Power supply ground. 7 GND Power Power supply ground. 8 GND Power Power supply ground. 9 Q5 Output LVCMOS/LVTTL clock output. 7typical output impedance. 10 Q6 Output LVCMOS/LVTTL clock output. 7typical output impedance. 11 Q7 Output LVCMOS/LVTTL clock output. 7typical output impedance. 12 CLK Input Pulldown LVCMOS/LVTTL clock input / 5V tolerant. 13 V Power Core supply pin. DD 14 Q8 Output LVCMOS/LVTTL clock output. 7typical output impedance. 15 Q9 Output LVCMOS/LVTTL clock output. 7typical output impedance. 16 Q10 Output LVCMOS/LVTTL clock output. 7typical output impedance. 17 GND Power Power supply ground. 18 GND Power Power supply ground. 19 GND Power Power supply ground. 20 Q11 Output LVCMOS/LVTTL clock output. 7typical output impedance. 21 Q12 Output LVCMOS/LVTTL clock output. 7typical output impedance. 22 V Power Q8 through Q15 output supply pin. DD2 23 V Power Q8 through Q15 output supply pin. DD2 24 V Power Q8 through Q15 output supply pin. DD2 25 Q13 Output LVCMOS/LVTTL clock output. 7typical output impedance. 26 Q14 Output LVCMOS/LVTTL clock output. 7typical output impedance. 27 Q15 Output LVCMOS/LVTTL clock output. 7typical output impedance. Output enable. When low forces outputs Q8 through Q15 to HiZ state. 28 OE2 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. Output enable. When low forces outputs Q0 through Q7 to HiZ state. 29 OE1 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. 30 Q0 Output LVCMOS/LVTTL clock output. 7typical output impedance. 31 Q1 Output LVCMOS/LVTTL clock output. 7typical output impedance. 32 Q2 Output LVCMOS/LVTTL clock output. 7typical output impedance. NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values. LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER 2 REVISION B 08/25/14