FemtoClock NG Crystal-to-HCSL 841654 Clock Generator DATASHEET GENERAL DESCRIPTION FEATURES The 841654 is an optimized PCIe and sRIO clock generator. Four differential HCSL clock outputs: con gurable for PCIe (100MHz) and sRIO (100MHz or 125MHz) clock signals The device uses a 25MHz parallel crystal to generate 100MHz One REF OUT LVCMOS/LVTTL clock output and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase Selectable crystal oscillator interface, 25MHz, 18pF parallel reso- jitter (< 1ps rms) suitable to clock components requiring precise and nant crystal or LVCMOS/LVTTL single-ended reference low-jitter PCIe or sRIO or both clock signals. Designed for telecom, clock input networking and industrial applications, the 841654 can also drive the Supports the following output frequencies: high-speed sRIO and PCIe SerDes clock inputs of communication 100MHz or 125MHz processors, DSPs, switches and bridges. VCO: 500MHz PLL bypass and output enable RMS phase jitter at 100MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) Full 3.3V power supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT XTAL IN VDD IREF 1 28 QA0 1 0 OSC REF OUT 27 FSEL0 2 GND FSEL1 3 26 nQA0 XTAL OUT FemtoClock QA0 QB0 4 25 PLL 0 NA Pulldown VCO = 500MHz nQA0 24 nQB0 REF IN 5 QA1 1 VDDOA 6 23 VDDOB GND nQA1 GND 7 22 Pulldown REF SEL QB1 QA1 8 21 nQB1 20 nQA1 9 M = 20 MR/nOE QB0 10 19 nREF OE VDD IREF 11 18 BYPASS nQB0 12 17 XTAL IN REF IN NB XTAL OUT REF SEL 13 16 Pulldown QB1 15 GND VDDA 14 BYPASS Pulldown FSEL 0:1 nQB1 841654 Pulldown 28-Lead TSSOP MR/nOE 6.1mm x 9.7mm x 0.925mm REF OUT package body G Package Pullup Top View nREF OE 841654 REVISION A 4/20/15 1 2015 Integrated Device Technology, Inc.841654 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 18 V Power Core supply pins. DD Single-ended reference frequency clock output. 2 REF OUT Output LVCMOS/LVTTL interface levels. 3, 7, 15, 22 GND Power Power supply ground. 4, 5, QA0, nQA0, Ouput Differential Bank A output pairs. HCSL interface levels. 8, 9 QA1, nQA1 6V Power Output supply pin for Bank A outputs. DDOA Active low REF OUT enable/disable. See Table 3E. 10 nREF OE Input Pullup LVCMOS/LVTTL interface levels. Selects PLL operation/PLL bypass operation. 11 BYPASS Input Pulldown See Table 3C. LVCMOS/LVTTL interface levels. Single-ended PLL reference clock input. 12 REF IN Input Pulldown LVCMOS/LVTTL interface levels. Reference select. Selects the input reference source. 13 REF SEL Input Pulldown See Table 3B. LVCMOS/LVTTL interface levels. 14 V Power Analog supply pin. DDA XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, 16, 17 Input XTAL IN XTAL IN is the input. (PLL reference.) Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the differential outputs are in high impedance 19 MR/nOE Input Pulldown (HiZ). When logic LOW, the internal dividers and the differential outputs are enabled. See Table 3D. LVCMOS/LVTTL interface levels. 20, 21 nQB1, QB1 Output Differential Bank B output pairs. HCSL interface levels. 24, 25 nQB0, QB0 23 V Power Output supply pin for Bank B outputs. DDOB FSEL1, 26, 27 Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels. FSEL0 HCSL current reference external resistor output. A xed precision resistor (RREF = 475) from this pin to ground provides a reference current used 28 IREF Output for differential current-mode QA 0:1 /nQA 0:1 and QB 0:1 /nQB 0:1 clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input PullupResistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN FEMTOCLOCKS CRYSTAL-TO-HCSL 2 REVISION A 4/20/15 CLOCK GENERATOR