FB SEL FemtoClock Crystal-to- 3.3V LVPECL 843252 Frequency Synthesizer Datasheet General Description Features The 843252 is a 2 differential output LVPECL Synthesizer designed Two differential LVPECL output pairs to generate Ethernet reference clock frequencies. Using a 25MHz, Using a 25MHz crystal, the two output banks can be 18pF parallel resonant crystal, the following frequencies can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz generated based on the settings of 4 frequency select pins Crystal oscillator interface (SELA 1:0 , SELB 1:0 ): 625MHz, 312.5MHz, 156.25MHz, and VCO frequency: 490MHz 680MHz 125MHz. RMS Phase Jitter 156.25MHz, (1.875MHz 20MHz) using a The two banks have their own dedicated frequency select pins and 25MHz crystal: 0.47ps (typical) can be independently set for the frequencies mentioned above. The Full 3.3V supply mode rd 843252 IDTs 3 generation low phase noise VCO technology and 0C to 70C ambient operating temperature can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843252 is packaged in a small Industrial temperature available upon request 16-pin TSSOP package. Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 2 Pullup XTAL IN SELA 0:1 nQB 1 16 2 XTAL OUT QB 15 0 0 1 VCCO B 3 14 VEE QA 0 1 2 SELB1 13 SELA1 4 nQA 1 0 3 XTAL IN SELB0 12 SELA0 1 1 4 (default) 5 Phase VCO OSC VCCO A 6 11 VCC 490MHz - 680MHz Detector 0 0 2 XTAL OUT QB QA 7 10 VCCA 0 1 4 nQA 8 9 nQB 1 0 5 1 1 8 (default) Feedback Divider 843252 0 = 25 (default) 16-Lead TSSOP 1 = 32 4.4mm x 5.0mm x 0.925mm package body Pulldown FB SEL G Package 2 Pullup SELB 0:1 2016 Integrated Device Technology, Inc. 1 Revision B, January 20, 2016843252 Datasheet Pin Description and Pin Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 2 nQB, QB Output Bank B differential output pair. LVPECL interface levels. 3V Power Output supply pin for QB, nQB outputs. CCO B 4, SELB1, Input Pullup Division select pins for Bank B. LVCMOS/LVTTL interface levels. 5 SELB0 6V Power Output supply pin for QA, nQA outputs. CCO A 7, 8 QA, nQA Output Bank A differential output pair. LVPECL interface levels. Feedback divide select. When LOW, the feedback divider is set for 25. When HIGH, 9 FB SEL Input Pulldown the feedback divider is set for 32. LVCMOS/LVTTL interface levels. 10 V Power Analog supply pin. CCA 11 V Power Core supply pin. CC 12, SELA0, Input Pullup Division select pins for Bank A. LVCMOS/LVTTL interface levels. 13 SELA1 14 V Power Negative supply pin. EE 15, XTAL OUT Input Crystal oscillator interface XTAL IN is the input, XTAL OUT is the output. 16 XTAL IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc. 2 Revision B, January 20, 2016