FemtoClock Crystal-to-LVDS ICS844011 Clock Generator DATA SHEET General Description Features The ICS844011 is a Fibre Channel Clock Generator. The One differential LVDS clock output pair ICS844011 uses an 18pF parallel resonant crystal. For Fibre Crystal interface designed for 18pF parallel resonant crystals Channel applications, a 26.5625MHz crystal is used. The VCO range: 490MHz 680MHz ICS844011 has excellent <1ps phase jitter performance, over the RMS phase jitter 106.25MHz, using a 26.5625MHz crystal 637kHz - 10MHz integration range. The ICS844011 is packaged in a (637kHz - 10MHz): 0.97ps (typical) small 8-pin TSSOP, making it ideal for use in systems with limited RMS phase jitter 100MHz, (637kHz - 10MHz): board space. 0.77ps (typical) Full 3.3V or 2.5V operating supply Available in lead-free (RoHS 6) package 0C to 70C ambient operating temperature Common Configuration Table Fibre Channel Inputs Crystal Frequency (MHz) M N Multiplication Value M/N Output Frequency (MHz) 26.5625 24 6 4 106.25 25 24 6 4 100 Block Diagram Pin Assignment 1 8 VDD VDDA Pullup OE GND 2 7 Q nQ XTAL OUT 3 6 OE XTAL IN 4 5 XTAL IN Q VCO Phase OSC N = 6 (fixed) ICS844011 490MHz - 680MHz nQ Detector XTAL OUT 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body M = 24 (fixed) G Package Top View ICS844011AG REVISION A AUGUST 27, 2012 1 2012 Integrated Device Technology, Inc. ICS844011 Data Sheet FEMTOCLOCK CRYSTAL-TO-LVDS CLOCK GENERATOR Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1V Power Analog power supply. DDA 2GND Power Power supply ground. 3, XTAL OUT, Input Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the output. 4 XTAL IN 5 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential clock output. LVDS interface levels. 8V Power Core supply pin. DD NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP Function Table Table 3. OE Control Function Table Input OE Output Enable 0 Output Q, nQ pair is disabled in high-impedance state. 1 (default) Output Q, nQ is enabled. ICS844011AG REVISION A AUGUST 27, 2012 2 2012 Integrated Device Technology, Inc.