nDATA OUT OC-12/STM-4 AND OC-3/STM-1 894D115I-04 Clock/Data Recovery Device Data Sheet General Description Features The 894D115I-04 is a clock and data recovery circuit. The device Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The Input: NRZ data (622.08 or 155.52 Mbit/s) output signals of the device are the recovered clock and retimed Output: clock signal (622.08MHz or 155.52MHz) and retimed data signals. Input and output are differential signals for best data signal at 622.08 or 155.52 Mbit/s signal integrity and to support high clock and data rates. All control Internal PLL for clock generation and clock recovery inputs and outputs are single-ended signals. An internal PLL is Differential inputs can accept LVPECL levels used for clock generation and recovery. An external clock input is provided to establish an initial operating frequency of the clock Differential LVDS data and clock outputs recovery PLL and to provide a clock reference in the absence of Lock reference input and PLL lock output serial input data. The device supports a signal detect input and a 19.44MHz reference clock input lock detect output. A bypass circuit is provided to facilitate factory Full 3.3V supply mode tests. -40C to 85C operating temperature Available in lead-free (RoHS 6) package See 894D115I for a clock/data recovery circuit with a TSSOP EPAD package and LVPECL outputs See 894D115I-01 for a clock/data recovery circuit with LVPECL outputs Block Diagram Pin Assignment CAP V VDDA DDA 1 20 2 19 GND PLL DATA IN nCAP nDATA IN 3 18 CAP GND PLL 4 17 nCAP LOCK DET 5 16 BYPASS STS12 6 15 SD Pulldown DATA IN REF CLK DATA OUT 7 14 PLL Pullup/Pulldown nDATA IN LOCK REFN 8 13 GND CLK OUT 9 12 V 10 11 nCLK OUT DD 894D115I-04 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm DATA OUT package body 0 nDATA OUT G Package Pulldown REF CLK Top View 1 CLK OUT Pulldown STS12 Pulldown SD nCLK OUT Pullup LOCK REFN LOCK DET Pulldown BYPASS 2016 Integrated Device Technology, Inc 1 Revision C January 27, 2016894D115I-04 Data Sheet Functional Description The 894D115I-04 is designed to extract the clock from a This will enable the use of the SD (signal detect) and the NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input LOCK REFN (lock-to-reference) inputs to accept loss of signal data signals. The output signals are the recovered clock and status information from electro-optical receivers. Please refer to retimed data signals. The device contains an integrated PLL for Figure 1, Signal Detect/PLL Bypass Operation Control Diagram, clock generation and to lock the output clock to the input data for details. stream. The PLL attempts to lock to the reference clock input The lock detect output (LOCK DET) can be used to monitor the (REF CLK) in absence of the serial data stream or if it is forced to operating state of the clock/data recovery circuit. LOCK DET is by the control inputs LOCK REFN or SD. The output clock set to logic low level when the internal oscillator of the PLL and frequency is controlled by the STS12 input. The output frequency the reference clock (REF CLK) deviate from each other by more is 622.08MHz in STM-4/OC-12/STS-12 mode and 155.52MHz in than 500ppm, or when the CDR is forced to lock the REF CLK STM-1/OC-3/STS-3 mode. input by the LOCK REFN or SD control input. LOCK DET is set The 894D115I-04 will maintain an output (CLK OUT/ nCLK OUT) to high when the PLL is locked to the input data stream and frequency deviation of less than 500ppm with respect to the indicates valid clock and data output signals. REF CLK reference frequency in a loss of signal state (LOS). The BYPASS pin should be set to logic low state in all During the LOS state, the data outputs (DATA OUT/ applications. BYPASS set to logic high state is used during factory nDATA OUT) are held at logic low state. An LOS state of the test. In BYPASS mode (BYPASS and STS12 are at logic high 894D115I-04 is given when BYPASS is set to the logic low state state), the internal PLL is bypassed and the inverted REF CLK and either one of the SD or LOCK REFN inputs are at a logic low input signal is output at CLK OUT/nCLK OUT. state. Pulldown DATA OUT DATA IN Pullup/Pulldown nDATA IN nDATA OUT PLL Clock 0 CLK OUT (on-chip) nCLK OUT Pulldown REF CLK 1 Pulldown STS12 Pulldown BYPASS Pullup LOCK REFN LOS (on-chip) Pulldown SD Figure 1. Signal Detect/PLL BYPASS Operation Control Diagram 2016 Integrated Device Technology, Inc 2 Revision C January 27, 2016