PC MAIN CLOCK - CK540 9UMS9001 Features/Benefits: Recommended Application: Supports Dothan ULV CPUs with 100 and Calistoga Based Ultra-Mobile PC (UMPC) 133 MHz CPU outputs Output Features: Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins 2 - CPU Low Power differential push-pull pairs PCI SRC and CPU STOP inputs for power 1 - ITP low power differential push-pull pair manangment 4 - SRC low power differential push-pull pairs Fully integrated Vreg 1 - LCD100 SSCD low power differential Integrated series resistors on differential push-pull pair outputs 1 - DOT96 low power differential push-pull Supports split rail operation for maximum pair power savings 3 - PCI, 33MHz Also runs from single 3.3V rail 1 - USB, 48MHz 1.05V-3.3V support for differential VDDIO 1 - REF, 14.31818MHz Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 X2 1 42 CLKREQ2 X1 2 41 CLKREQ3 VDDREFIO 3.3 3 40 VDDCORE 3.3 REF0 4 39 SRC3T LPRS 538 SDATA SRC3C LPRS 6 SCLK 37 SRC2T LPRS TEST SEL 7 36 SRC2C LPRS ICS9UMS9001 TEST MODE 8 35 VDDIO SRC PCI STOP 9 34 GNDSRC VDDIO PCI3.3 10 33 SRC1T LPRS PCI0 11 32 SRC1C LPRS PCI1 12 31 SRC0T LPRS PCI F2 13 30 SRC0C LPRS GNDPCI 14 29 CLKREQ0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-pin MLF IDT PC MAIN CLOCK - CK540 1247C06/16/11 1 GND48 GNDREF USB 48MHz FSLC CK PWRGD /PD VDD48IO 3.3 VDDCPUPLL 3.3 VDD48PLL 3.3 VDDIO 96Mhz CPU0T LPRS DOT96C LPRS CPU0C LPRS GNDCPU DOT96T LPRS VDDIO CPU GND GND CPU1T LPRS LCD100C LPRS CPU1C LPRS CPUITPT LPRS LCD100T LPRS CPUITPC LPRS VDDIO LCD VDDLCDPLL 3.3 CPU STOP CLKREQ1 FSLB9UMS9001 PC MAIN CLOCK - CK540 Advance Information Pin Description PIN PIN NAME TYPE DESCRIPTION 1 X2 OUT Crystal output, nominally 14.318MHz. 2 X1 IN Crystal input, Nominally 14.318MHz. 3 VDDREFIO 3.3 PWR Power pin for the REF output and crystal oscillator. 3.3V nominal. 4 REF0 OUT 3.3V 14.318MHz reference clock 5 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 6 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 3.3V input that puts the part in test mode. This is a realtime input. See the Test Clarification Table for 7TEST SEL IN details. 8 TEST MODE IN When Test mode is selected, this chooses either hi-Z or REF/N for the outputs. 9 PCI STOP IN 3.3V tolerant input that stops all PCI and SRC clocks, except those set to be free running. 10 VDDIO PCI3.3 PWR 3.3V power supply for the PCI outputs 11 PCI0 OUT 3.3V PCI clock output. 12 PCI1 OUT 3.3V PCI clock output. 13 PCI F2 OUT Free running 3.3V PCI clock output 14 GNDPCI PWR Ground for PCI output clocks. 15 GND48 PWR Ground for the USB clock. 16 USB 48MHz OUT Fixed 3.3V 48MHz USB clock output 17 VDD48IO 3.3 PWR 3.3V Power supply for the 48MHz output 18 VDD48PLL 3.3 PWR 3.3V Power supply for the 48/96MHz PLL 19 VDDIO 96Mhz PWR Power supply for DOT96 output. VDD IO = 1.05 to 3.3V +/-5%. Complement side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external 20 DOT96C LPRS OUT series resistor required). True side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external series 21 DOT96T LPRS OUT resistor required). 22 GND PWR Ground for 96MHz output 23 GND PWR Ground for LCD 100 MHz output. Complement side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated 24 LCD100C LPRS OUT (No external series resistor required). True side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No 25 LCD100T LPRS OUT external series resistor required). 26 VDDIO LCD PWR Power supply for LCD100 output. VDD IO = 1.05 to 3.3V +/-5%. 27 VDDLCDPLL 3.3 PWR 3.3V Power supply for the LCD100 Spreading PLL Clock request input for SRC output pair 1. See the SRC, LCD, DOT Power Management Table for 28 CLKREQ1 IN details IDT PC MAIN CLOCK - CK540 1247C06/16/11 2