482067A

ST6215C ST6225C 8-bit MCUs with A/D converter, two timers, oscillator safeguard & safe reset Memories 2K or 4K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection 64 bytes RAM Clock, Reset and Supply Management Enhanced reset system Low Voltage Detector (LVD) for Safe Reset PDIP28 Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO) Oscillator Safeguard (OSG) 2 Power Saving Modes: Wait and Stop S028 Interrupt Management 4 interrupt vectors plus NMI and RESET 20 external interrupt lines (on 2 vectors) 1 external non-interrupt line 20 I/O Ports SS0P28 20 multifunctional bidirectional I/O lines 16 alternate function lines 4 high sink outputs (20mA) 2 Timers Configurable watchdog timer 8-bit timer/counter with a 7-bit prescaler Analog Peripheral 8-bit ADC with 16 input channels CDIP28W Instruction Set (See Section 12.5 for Ordering Information) 8-bit data manipulation 40 basic instructions Development Tools 9 addressing modes Full hardware/software development package Bit manipulation Device Summary Features ST6215C ST6225C Program memory - bytes 2K 4K RAM - bytes 64 Operating Supply 3.0V to 6V Clock Frequency 8MHz Max Operating Temperature -40C to +125C Packages PDIP28 / SO28 / SSOP28 January 2009 Rev 4 1/105 1Table of Contents 1 INTRODUCTION 6 2 PIN DESCRIPTION 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES 9 3.1 MEMORY AND REGISTER MAPS 9 3.1.1 Introduction 9 3.1.2 Program Space 11 3.1.3 Readout Protection . 11 3.1.4 Data Space . 11 3.1.5 Stack Space . 11 3.1.6 Data ROM Window Mechanism 13 3.2 PROGRAMMING MODES 15 3.2.1 Program Memory . 15 3.2.2 EPROM Erasing 15 3.3 OPTION BYTES . 16 4 CENTRAL PROCESSING UNIT . 17 4.1 INTRODUCTION . 17 4.2 MAIN FEATURES 17 4.3 CPU REGISTERS 17 5 CLOCKS, SUPPLY AND RESET 19 5.1 CLOCK SYSTEM . 19 5.1.1 Main Oscillator . 20 5.1.2 Oscillator Safeguard (OSG) . 21 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . 22 5.1.4 Register Description . 22 5.2 LOW VOLTAGE DETECTOR (LVD) 23 5.3 RESET . 24 5.3.1 Introduction . 24 5.3.2 RESET Sequence 24 5.3.3 RESET Pin 25 5.3.4 Watchdog Reset . 26 5.3.5 LVD Reset 26 6 INTERRUPTS . 27 6.1 INTERRUPT RULES AND PRIORITY MANAGEMENT . 29 6.2 INTERRUPTS AND LOW POWER MODES 29 6.3 NON MASKABLE INTERRUPT 29 6.4 PERIPHERAL INTERRUPTS . 29 6.5 EXTERNAL INTERRUPTS (I/O PORTS) 30 6.5.1 Notes on using External Interrupts 30 6.6 INTERRUPT HANDLING PROCEDURE . 31 6.6.1 Interrupt Response Time . 31 6.7 REGISTER DESCRIPTION . 32 105 7 POWER SAVING MODES . 33 7.1 INTRODUCTION . 33 2/105 2