M48T128Y 5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal BCD coded year, month, day, date, hours, minutes, and seconds Automatic power-fail chip deselect and WRITE 32 protection 1 WRITE protect voltage V = 4.5 to 5.5 V 4.1 V V 4.5 V PMDIP32 module CC PFD (V = power-fail deselect voltage) PFD Conventional SRAM operation unlimited WRITE cycles Software-controlled clock calibration for high accuracy applications 10 years of data retention and clock operation in the absence of power Self-contained battery and crystal in the DIP package Pin and function compatible with JEDEC standard 128 K x 8 SRAMs RoHS compliant Lead-free second level interconnect September 2011 Doc ID 5746 Rev 7 1/23 This is information on a product still in production but not recommended for new designs. www.st.com 1 Obsolete Product(s) - Obsolete Product(s)Contents M48T128Y Contents 1 Description . 5 2 Operation modes 7 2.1 READ mode 8 2.2 WRITE mode . 9 2.3 Data retention mode . 10 3 Clock operations . 11 3.1 Reading the clock . 11 3.2 Setting the clock 11 3.3 Stopping and starting the oscillator . 11 3.4 Calibrating the clock . 12 3.5 V noise and negative going transients . 14 CC 4 Maximum ratings . 15 5 DC and AC parameters 16 6 Package mechanical data 19 7 Environmental information . 20 8 Part numbering 21 9 Revision history . 22 2/23 Doc ID 5746 Rev 7 Obsolete Product(s) - Obsolete Product(s)