ST7LITEU05 ST7LITEU09 8-bit MCU with single voltage Flash memory, ADC, timers Datasheet - production data Features Memories 2K Bytes single voltage Flash program SO8 memory with readout protection, in-circuit DIP8 150 and in-application programming (ICP and DFN8 IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55 C A/D converter 128 bytes RAM 10-bit resolution for 0 to VDD 128 bytes data EEPROM. 300K write/erase 5 input channels cycles guaranteed, data retention: 20 years Instruction set at 55 C 8-bit data manipulation Clock, reset and supply management 63 basic instructions with illegal opcode 3-level low voltage supervisor (LVD) and detection auxiliary voltage detector (AVD) for safe 17 main addressing modes power- on/off procedures 8 x 8 unsigned multiply instruction Clock sources: internal trimmable 8-MHz RC oscillator, internal low power, low Development tools frequency RC oscillator or external clock Full hardware/software development Five Power Saving Modes: Halt, Auto- package Wakeup from Halt, Active-halt, Wait and Debug module Slow Interrupt management 11 interrupt vectors plus TRAP and RESET 5 external interrupt lines (on 5 vectors) I/O Ports 5 multifunctional bidirectional I/O lines 1 additional output line 6 alternate function lines 5 high sink outputs 2 timers One 8-bit lite timer (LT) with prescaler including: watchdog, 1 realtime base and 1 input capture One 12-bit auto-reload timer (AT) with output compare function and PWM October 2016 DocID13474 Rev 3 1/146 This is information on a product in full production. www.st.comContents ST7LITEU05 ST7LITEU09 Contents 1 Description 12 2 Pin description 13 3 Register & memory map . 17 4 Flash program memory . 20 4.1 Introduction . 20 4.2 Main features 20 4.3 Programming modes 20 4.3.1 In-circuit programming (ICP) . 20 4.3.2 In Application Programming (IAP) . 21 4.4 ICC interface 21 4.5 Memory protection 23 4.5.1 Readout protection 23 4.5.2 Flash write/erase protection 23 4.6 Related documentation 23 4.7 Register description . 24 4.7.1 Flash control/status register (FCSR) . 24 5 Data EEPROM . 25 5.1 Introduction . 25 5.2 Main features 25 5.3 Memory access 25 5.3.1 Read operation (E2LAT=0) 26 5.3.2 Write operation (E2LAT=1) 26 5.4 Power saving modes 27 5.4.1 Wait mode . 27 5.4.2 Active-halt mode 27 5.4.3 Halt mode . 27 5.5 Access error handling 27 5.6 Data EEPROM readout protection 28 5.7 Register description . 28 2/146 DocID13474 Rev 3