STGAP2SCMTR STMicroelectronics

STGAP2S Datasheet Galvanically isolated 4 A single gate driver Features High voltage rail up to 1700 V Driver current capability: 4 A sink/source 25C dV/dt transient immunity 100 V/ns in full temperature range Overall input-output propagation delay: 75 ns Separate sink and source option for easy gate driving configuration 4 A Miller CLAMP dedicated pin option UVLO function Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shut-down protection Standby function Narrow body SO8 Application Motor driver for home appliances, factory automation, industrial drives and fans. 600/1200 V inverters Battery chargers Induction heating Welding UPS Product status link Power supply units STGAP2S DC-DC converters Power Factor Correction Product label Description The STGAP2S is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates UVLO and thermal shutdown protection functions to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross- conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption. DS12541 - Rev 2 - July 2021 www.st.com For further information contact your local STMicroelectronics sales office.STGAP2S Block diagram 1 Block diagram Figure 1. Block diagram - separated outputs option VH VDD I UVLO S IN+ VH O Floating Level GON Section Shifter L Control Control A Logic Logic T GOFF IN- I O GNDISO N Floating ground GND Figure 2. Block diagram - single output and Miller clamp option VDD VH I UVLO S IN+ VH O Level Floating GOUT Section Shifter L Control Control A Logic Logic T CLAMP IN- I O GNDISO N Floating ground A + GND VCLAMPth DS12541 - Rev 2 page 2/23