W25Q20EWSNIG

W25Q20EW 1.8V 2M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS, DUAL AND QUAD SPI Publication Release Date: August 22, 2017 - 1 - -Revision I W25Q20EW Table of Contents 1. GENERAL DESCRIPTION ......................................................................................................... 5 2. FEATURES ................................................................................................................................. 5 4. PACKAGE TYPES AND PIN CONFIGURATIONS..................................................................... 6 4.1 Pin Configuration SOIC 150-mil and VSOP 150-mil....................................................... 6 4.2 PAD Configuration USON 2x3-mm/ USON 4x3-mm ...................................................... 6 4.3 Pin Description SOIC/ VSOP 150-mil, USON 2x3-mm/4x3-mm .................................... 6 4.4 Ball Configuration WLCSP .............................................................................................. 7 4.5 Ball Description WLCSP ................................................................................................. 7 5. PIN DESCRIPTIONS .................................................................................................................. 8 5.1 Chip Select (/CS) ............................................................................................................ 8 5.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ............................... 8 5.3 Write Protect (/WP) ......................................................................................................... 8 5.4 HOLD (/HOLD)................................................................................................................ 8 5.5 Serial Clock (CLK) .......................................................................................................... 8 6. BLOCK DIAGRAM ...................................................................................................................... 9 7. FUNCTIONAL DESCRIPTION.................................................................................................. 10 7.1 SPI OPERATIONS ....................................................................................................... 10 7.1.1 Standard SPI Instructions ............................................................................................... 10 7.1.2 Dual SPI Instructions ...................................................................................................... 10 7.1.3 Quad SPI Instructions ..................................................................................................... 10 7.1.4 Hold Function .................................................................................................................. 10 7.2 WRITE PROTECTION .................................................................................................. 11 7.2.1 Write Protect Features .................................................................................................... 11 8. CONTROL AND STATUS REGISTERS ................................................................................... 12 8.1 STATUS REGISTER .................................................................................................... 12 8.1.1 BUSY .............................................................................................................................. 12 8.1.2 Write Enable Latch (WEL) .............................................................................................. 12 8.1.3 Block Protect Bits (BP2, BP1, BP0) ................................................................................ 12 8.1.4 Top/Bottom Block Protect (TB) ....................................................................................... 12 8.1.5 Sector/Block Protect (SEC) ............................................................................................. 12 8.1.6 Complement Protect (CMP) ............................................................................................ 12 8.1.7 Protection and Special One time Programming Setting .................................................. 13 8.1.8 Erase/Program Suspend Status (SUS) ........................................................................... 14 8.1.9 Security Register Lock Bits (LB 3:0 ) Volatile/Non-Volatile OTP Writable ................. 14 8.1.1 Quad Enable (QE) .......................................................................................................... 14 8.1.2 Status Register Memory Protection (CMP = 0) ............................................................... 16 8.1.3 Status Register Memory Protection (CMP = 1) ............................................................... 17 8.2 INSTRUCTIONS ........................................................................................................... 18 8.2.1 Manufacturer and Device Identification ........................................................................... 18 (1) 8.2.2 Instruction Set Table 1 (Erase, Program Instructions) ................................................. 19 8.2.3 Instruction Set Table 2 .................................................................................................... 19 8.3 Instruction Descriptions ................................................................................................ 21 8.3.1 Write Enable (06h) .......................................................................................................... 21 Publication Release Date: August 22, 2017 - 2 - -Revision I