AS4C128M16D3L-12BCN

AS4C128M16D3 REVISION HISTORY AS4C128M16D3 96-ball FBGA PACKAGE Revision Description Issue Date Rev. 1.0 Initial Issue February 2014 Rev. 2.0 Typing error in Table 2 page 2 incorrect temperature range June 2014 amended to: - Commercial (Extended) (0 ~ 95C) - Industrial (-40 ~ 95C) Rev 3.0 Updated Table 11. Recommended DC Operating Conditions page 21 August 2014 Added CL=5 & CL=6 to Table 18 page 26 Confidential 1 Rev. 3.0 Aug. /2014 AS4C128M16D3 2Gb (128M x 16 bit) DDR3 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 3.0, Aug. /2014) Overview Features JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is Power supplies: V & V = +1.5V 0.075V DD DDQ internally configured as an eight bank DRAM. Operating temperature: The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 - Commercial (0 ~ 95C) bank devices. These synchronous devices achieve high - Industrial (-40 ~ 95C) speed double-data-rate transfer rates of up to 1600 Supports JEDEC clock jitter specification Mb/sec/pin for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3 Fast clock rate: 800MHz DRAM key features and all of the control and address Differential Clock, CK & CK inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the Bidirectional differential data strobe cross point of differential clocks (CK rising and CK - DQS & DQS falling). All I/Os are synchronized with differential DQS 8 internal banks for concurrent operation pair in a source synchronous fashion. 8n-bit prefetch architecture These devices operate with a single 1.5V 0.075V Internal pipeline architecture power supply and are available in BGA packages. Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 TC +85 3.9s +85 TC +95 Write Leveling OCD Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 9 x 13 x 1.2mm FBGA package - All parts are ROHS Compliant Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR3-1600 800 MHz 11 13.75 13.75 Table 2 Ordering Information for ROHS Compliant Products Product part No Org Temperature Package AS4C128M16D3-12BCN 128M x 16 Commercial(Extended) 96-ball 0C to 95C FBGA AS4C128M16D3-12BIN 128M x 16 Industrial 96-ball -40C to 95C FBGA Confidential 2 Rev. 3.0 Aug. /2014