Product Information

MT48LC64M8A2TG-75:IT:C

MT48LC64M8A2TG-75:IT:C electronic component of Alliance Memory

Datasheet
Alliance Memory DRAM 512M 3.3V 133MHz 64M x 8 IND TEMP
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 20.538 ea
Line Total: USD 20.54

1953 - Global Stock
Ships to you between
Mon. 27 May to Wed. 29 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

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1817 - WHS 1


Ships to you between Mon. 27 May to Wed. 29 May

MOQ : 1
Multiples : 1

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MT48LC64M8A2TG-75:IT:C
Alliance Memory

1 : USD 17.388
10 : USD 16.376
25 : USD 16.1115
108 : USD 14.352
216 : USD 13.754
540 : USD 13.754
1080 : USD 13.6965
2592 : USD 13.593
5076 : USD 13.225

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Additional Infomation About Product

512Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC128M4A2 32 Meg x 4 x 4 banks MT48LC64M8A2 16 Meg x 8 x 4 banks MT48LC32M16A2 8 Meg x 16 x 4 banks Options Marking Features Configurations PC100- and PC133-compliant 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 Fully synchronous all signals registered on positive 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 edge of system clock 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 Internal, pipelined operation column address can t Write recovery ( WR) be changed every clock cycle t 1 WR = 2 CLK A2 Internal banks for hiding row access/precharge 2 Plastic package OCPL Programmable burst lengths: 1, 2, 4, 8, or full page 54-pin TSOP II (400 mil) (standard) TG Auto precharge, includes concurrent auto precharge 54-pin TSOP II (400 mil) Pb-free P and auto refresh modes Timing cycle time Self refresh mode 7.5ns CL = 3 (PC133) -75 Auto refresh 3 7.5ns CL = 2 (PC133) -7E 64ms, 8192-cycle refresh (commercial and Self refresh industrial) Standard None LVTTL-compatible inputs and outputs 4 Low power L Single 3.3V 0.3V power supply Operating temperature range Commercial (0C to +70C) None Industrial (40C to +85C) IT Revision :C 1. See technical note TN-48-05 on Notes: Micron s Web site. 2. Off-center parting line. 3. Available on x4 and x8 only. 4. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Access Time Clock Speed Grade Frequency CL = 2 CL = 3 Setup Time Hold Time -7E 143 MHz 5.4ns 1.5ns 0.8ns -75 133 MHz 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns 1.5ns 0.8ns -75 100 MHz 6ns 1.5ns 0.8ns PDF: 09005aef809bf8f3 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 512Mb sdr.pdf - Rev. Q 12/12 EN 2000 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x4, x8, x16 SDRAM Features Table 2: Address Table 32 Meg Parameter 32 Meg x 4 32 Meg x 8 x 16 Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh count 8K 8K 8K Row addressing 8K A 12:0 8K A 12:0 8K A 12:0 Bank addressing 4 BA 1:0 4 BA 1:0 4 BA 1:0 Column 4K A 9:0 , A11, A12 2K A 9:0 , A11 1K A 9:0 addressing Table 3: 512Mb SDR Part Numbering Part Numbers Architecture Package MT48LC128M4A2P 128 Meg x 4 54-pin TSOP II MT48LC128M4A2TG 128 Meg x 4 54-pin TSOP II MT48LC64M8A2P 64 Meg x 8 54-pin TSOP II MT48LC64M8A2TG 64 Meg x 8 54-pin TSOP II MT48LC32M16A2P 32 Meg x 16 54-pin TSOP II MT48LC32M16A2TG 32 Meg x 16 54-pin TSOP II PDF: 09005aef809bf8f3 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 512Mb sdr.pdf - Rev. Q 12/12 EN 2000 Micron Technology, Inc. All rights reserved.

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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