CS2100CP-CZZ

CS2100-CP Fractional-N Clock Multiplier Features General Description Clock Multiplier / Jitter Reduction The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase Generates a Low Jitter 6 - 75 MHz Clock lock loop. The CS2100-CP is based on a hybrid ana- from a Jittery or Intermittent 50 Hz to 30 log-digital PLL architecture comprised of a unique MHz Clock Source combination of a Delta-Sigma Fractional-N Frequency Highly Accurate PLL Multiplication Factor Synthesizer and a Digital PLL. This architecture allows Maximum Error Less Than 1 PPM in High- for generation of a low-jitter clock relative to an exter- Resolution Mode nal noisy synchronization clock at frequencies as low IC / SPI Control Port as 50 Hz. The CS2100-CP supports both IC and SPI for full software control. Configurable Auxiliary Output The CS2100-CP is available in a 10-pin MSOP pack- Flexible Sourcing of Reference Clock age in Commercial (-10C to +70C) and Automotive External Oscillator or Clock Source (-40C to +85C) grades. Customer development kits Supports Inexpensive Local Crystal are also available for device evaluation. Please see Minimal Board Space Required Ordering Information on page 32 for complete details. No External Analog Loop-filter Components 3.3 V Timing Reference IC/SPI Frequency Reference IC / SPI Software Control Auxiliary PLL Output Output Lock Indicator 8 MHz to 75 MHz Fractional-N 6 to 75 MHz Low-Jitter Timing Frequency Synthesizer PLL Output Reference N 50 Hz to 30 MHz Digital PLL & Fractional Frequency N Logic Reference Output to Input Clock Ratio Copyright Cirrus Logic, Inc. 2010 MAY 10 (All Rights Reserved) CS2100-CP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 5 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 RECOMMENDED OPERATING CONDITIONS .................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8 PLL PERFORMANCE PLOTS ............................................................................................................... 9 CONTROL PORT SWITCHING CHARACTERISTICS- IC FORMAT ................................................. 10 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11 4. ARCHITECTURE OVERVIEW ............................................................................................................. 12 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12 4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................12 5. APPLICATIONS ................................................................................................................................... 14 5.1 Timing Reference Clock Input ........................................................................................................ 14 5.1.1 Internal Timing Reference Clock Divider ............................................................................... 14 5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 15 5.1.3 External Reference Clock (REF CLK) .................................................................................. 15 5.2 Frequency Reference Clock Input, CLK IN ................................................................................... 15 5.2.1 CLK IN Skipping Mode ......................................................................................................... 15 5.2.2 Adjusting the Minimum Loop Bandwidth for CLK IN ............................................................17 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 18 5.3.1 User Defined Ratio (RUD) ..................................................................................................... 18 5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 19 5.3.3 Effective Ratio (REFF) .......................................................................................................... 20 5.3.4 Ratio Configuration Summary ............................................................................................... 20 5.4 PLL Clock Output ........................................................................................................................... 21 5.5 Auxiliary Output .............................................................................................................................. 21 5.6 Clock Output Stability Considerations ............................................................................................ 22 5.6.1 Output Switching ................................................................................................................... 22 5.6.2 PLL Unlock Conditions .......................................................................................................... 22 5.7 Required Power Up Sequencing .................................................................................................... 22 6. SPI / IC CONTROL PORT ................................................................................................................... 22 6.1 SPI Control ..................................................................................................................................... 23 6.2 IC Control ...................................................................................................................................... 23 6.3 Memory Address Pointer ............................................................................................................... 25 6.3.1 Map Auto Increment .............................................................................................................. 25 7. REGISTER QUICK REFERENCE ........................................................................................................ 25 8. REGISTER DESCRIPTIONS ................................................................................................................ 26 8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 26 8.1.1 Device Identification (Device 4:0 ) - Read Only ..................................................................... 26 8.1.2 Device Revision (Revision 2:0 ) - Read Only ........................................................................ 26 8.2 Device Control (Address 02h) ........................................................................................................ 26 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 26 8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 26 8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 27 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 27 8.3.1 R-Mod Selection (RModSel 2:0 ) ...........................................................................................27 8.3.2 Auxiliary Output Source Selection (AuxOutSrc 1:0 ) ............................................................. 27 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 28 8.4 Global Configuration (Address 05h) ............................................................................................... 28 8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 28 2 DS840F2