PCI Express Jitter Attenuator 9DB306 Data Sheet GENERAL DESCRIPTION FEATURES The 9DB306 is a high performance 1-to-6 Differential-to- Six differential LVPECL output pairs LVPECL Jitter Attenuator designed for use in PCI Express One differential clock input systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a CLK and nCLK supports the following input types: low bandwidth, high phase noise PLL frequency synthesizer. In LVPECL, LVDS, LVHSTL, SSTL, HCSL these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from Maximum output frequency: 140MHz the PLL synthesizer and from the system board. The 9DB306 Input frequency range: 90MHz - 140MHz has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of VCO range: 450MHz - 700MHz the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum pro le. There is also Output skew: 135ps (maximum) a high bandwidth mode which sets the PLL bandwidth at 1MHz Cycle-to-Cycle jitter: 30ps (maximum) which will pass more spread spectrum modulation. RMS phase jitter 100MHz, (1.5MHz - 22MHz): 3ps (typical) For serdes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be 3.3V operating supply set for 125MHz instead of 100MHz by con guring the appropriate 0C to 70C ambient operating temperature frequency select pins (FS0:1). Output PCIEX0 will always run at the reference clock frequency (usually 100MHz) in desktop PC PCI Available in lead-free (RoHS 6) package Express Applications. Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 1 Disabled nOE0 0 Enabled VEE 1 28 VCC 27 PCIEXC0 PCIEXT1 2 0 PCIEXT0 PCIEXT0 PCIEXC1 3 26 5 nPCIEXC0 1 FS0 4 25 PCIEXT2 nCLK PCIEXC2 24 5 Buffer CLK 6 23 VCC PLL BW nOE0 7 22 VCCA nOE1 8 21 CLK Loop PCIEXT1 VEE VCC 20 Phase 0 9 0 4 VCO nCLK Filter nPCIEXC1 BYPASS PCIEXC3 10 19 Detector 1 5 FS1 PCIEXT2 PCIEXT3 11 18 PCIEXT5 nPCIEXC2 PCIEXC4 12 17 1 PCIEXC5 PCIEXT4 13 16 VCC VEE 15 FS0 14 5 9DB306 Internal Feedback 28-Lead TSSOP, 173-MIL PCIEXT3 4.4mm x 9.7mm x 0.925mm 0 0 5 nPCIEXC3 body package 1 4 L Package PCIEXT4 Top View nPCIEXC4 PCIEXT5 1 9DB306 nPCIEXC5 28-Lead, 209-MIL SSOP 5.3mm x 10.2mm x 1.75mm FS1 body package BYPASS F Package Top View 1 Disabled nOE1 0 Enabled 2016 Integrated Device Technology, Inc 1 Revision C February 18, 20169DB306 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 14, 20 V Power Negative supply pins. EE PCIEXT1, 2, 3 Output Differential output pairs. LVPECL interface levels. PCIEXC1 PCIEXT2, 4, 5 Output Differential output pairs. LVPECL interface levels. PCIEXC2 6, 9, 15, 28 V Power Core supply pins. CC Output enable. When HIGH, forces true outputs (PCIEXTx) to go LOW 7, 8 nOE0, nOE1 Input Pulldown and the inverted outputs (PCIEXCx) to go HIGH. When LOW, outputs are enabled. LVCMOS/LVTTL interface levels. PCIEXC3, 10, 11 Output Differential output pairs. LVPECL interface levels. PCIEXT3 PCIEXC4, 12, 13 Output Differential output pairs. LVPECL interface levels. PCIEXT4 PCIEXC5, 16, 17 Output Differential output pairs. LVPECL interface levels. PCIEXT5 18 FS1 Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Bypass select pin. When HIGH, the PLL is in bypass mode, and the 19 BYPASS Input Pulldown device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels. 21 V Power Analog supply pin. Requires 24 series resistor. CCA 22 PLL BW Input Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. 23 CLK Input Pulldown Non-inverting differential clock input. Pullup/ 24 nCLK Input Inverting differential clock input. V /2 default when left oating. CC Pulldown 25 FS0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. PCIEXT0, 26, 27 Output Differential output pairs. LVPECL interface levels. PCIEXC0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN TABLE 3A. RATIO OF OUTPUT FREQUENCY TO TABLE 3B. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS0 INPUT FREQUENCY FUNCTION TABLE, FS1 Inputs Outputs Inputs Outputs FS0 PCIEX0 PCIEX1 PCIEX2 FS1 PCIEX3 PCIEX4 PCIEX5 0 1 5/4 5/4 011 1 111 1 1 5/4 5/4 5/4 TABLE 3E. PLL BANDWIDTH TABLE 3F. PLL MODE TABLE 3C. OUTPUT ENABLE TABLE 3D. OUTPUT ENABLE FUNCTION TABLE FUNCTION TABLE FUNCTION TABLE, nOE0 FUNCTION TABLE, nOE1 Inputs Inputs Inputs Outputs Inputs Outputs Bandwidth PLL Mode PLL BW BYPASS nOE0 PCIEX0:2 nOE1 PCIEX3:5 0 Enabled 0 Enabled 0 500kHz 1 Disabled 1 Disabled 1 1MHz 0 Enabled 1 Disabled 2016 Integrated Device Technology, Inc 2 Revision C February 18, 2016