DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL MK2049-34A Description Features The MK2049-34A is a VCXO Phased Locked Loop (PLL) Packaged in 20-pin SOIC based clock synthesizer that accepts multiple input Pb (lead) free package frequencies. With an 8 kHz clock input as a reference, the 3.3 V + 5% operation MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the Fixed I/O phase relationship on all selections generation of clocks frequency-locked and phase-locked to Meets the TR62411, ETS300 011, and GR-1244 an 8 kHz backplane clock, simplifying clock synchronization specification for MTIE, Pull-in/Hold-in Range, Phase in communications systems. The MK2409-34 can also Transients, and Jitter Generation for Stratum 3, 4, and 4E accept a T1 or E1 input clock and provide the same output Accepts multiple inputs: 8 kHz backplane clock, Loop for loop timing. All outputs are frequency locked together Timing frequencies, or 10 to 36 MHz and to the input. Locks to 8 kHz + 100 ppm (External mode) This part also has a jitter-attenuated Buffer capability. In this Buffer Mode allows jitter attenuation of 10 to 36 MHz mode, the MK2049-34A is ideal for filtering jitter from 27 input and x1/x0.5 or x2/x4 outputs MHz video clocks or other clocks with high jitter. Exact internal ratios enable zero ppm error IDT can customize these devices for many other different frequencies. Output clock rates include T1, E1, T3, E3, ISDN, xDSL, and the OC3 submultiples See the MK2049-01, -02, and -03 for more selections at 5 V Industrial temperature range Block Diagram EXTERNAL PULLABLE CRYSTAL (external loop filter) INPUT REFERENCE VCXO-BASED FREQUENCY CLOCK MULTIPLYING CLOCK OUTPUT PLL (TYPICALLY 8KHZ) PLL (MASTER CLOCK 2 CLOCK OUTPUT / 2 GENERATOR) 8 KHZ (REGENERATED) 4 FREQUENCY SELECT IDT 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 1 MK2049-34A REV E 051310MK2049-34A 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL VCXO AND SYNTHESIZER Pin Assignment FS1 1 20 FS0 X2 2 19 RES X1 3 18 CAP2 VDD 4 17 GND FCAP 5 16 CAP1 VDD 6 15 VDD GND 7 14 GND CLK 8 13 ICLK CLK/2 9 12 FS3 8k 10 11 FS2 20-pin (300) mil SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 3. 2 X2 XO Crystal connection. Connect to a MHz crystal as shown in table on page 3. 3 X1 XI Crystal connection. Connect to a MHz crystal as shown in table on page 3. 4 VDD Power Power supply. Connect to +3.3 V. 5 FCAP Filter capacitor. Connect a 1000 pF ceramic capacitor to ground. 6 VDD Power Power supply. Connect to +3.3 V. 7 GND Power Connect to ground 8 CLK Output Clock output determined by status of FS3:0 per tables on page 3. 9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of CLK. 10 8k Output Recovered 8 kHz clock output. 11 FS2 Input Frequency select 2. Determines CLK input/outputs per tables on page 3. 12 FS3 Input Frequency select 3. Determines CLK input/outputs per tables on page 3. 13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock. 14 GND Power Connect to ground. 15 VDD Power Power Supply. Connect to +3.3 V. 16 CAP1 Loop Connect the loop filter ceramic capacitors and resistor between this pin and Filter CAP2. 17 GND Power Connect to ground. 18 CAP2 Loop Connect the loop filter ceramic capacitors and resistor between this pin and 19 RES Connect a 10-200k resistor to ground. Contact IDT for recommended value for your application. 20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 3. IDT / 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 2 MK2049-34A REV E 051310