Product Information

MK2058-01SILF

MK2058-01SILF electronic component of Renesas

Datasheet
Clock Synthesizer / Jitter Cleaner COMMUNICATIONS CLOCK JITTER ATTENUATOR

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 143.073 ea
Line Total: USD 143.07

2 - Global Stock
Ships to you between
Thu. 02 May to Wed. 08 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2 - Global Stock


Ships to you between Thu. 02 May to Wed. 08 May

MOQ : 1
Multiples : 1
1 : USD 144.775
5 : USD 117.1875
15 : USD 112.675
40 : USD 108.3375
150 : USD 104.175

     
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DATASHEET COMMUNICATIONS CLOCK JITTER ATTENUATOR MK2058-01 Description Features The MK2058-01 is a VCXO (Voltage Controlled Crystal Excellent jitter attenuation for telecom clocks Oscillator) based clock jitter attenuator designed for system Also serves as a general purpose clock jitter attenuator clock distribution applications. This monolithic IC, combined for distributed system clocks and recovered data or video with an external inexpensive quartz crystal, can be used to clocks replace a more costly hybrid VCXO retiming module. The 2:1 Input MUX for input reference clocks device accepts and outputs the same clock frequency in selectable ranges covering 4 kHz to 27 MHz. A dual input No switching glitches on output mux is also provided. VCXO-based clock generation offers very low jitter and phase noise generation By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked Output clock is phase and frequency locked to the to the input clock. Through selection of external loop filter selected input reference clock components, the PLL loop bandwidth and damping factor Fixed input to output phase relationship can be tailored to meet system clock requirements. A loop +115ppm minimum crystal frequency pullability range, bandwidth down to the Hz range is possible. using recommended crystal Industrial temperature range Low power CMOS technology 20-pin SOIC package Pb (lead) free package Single 3.3 V power supply Block Diagram Pullable Crystal VDD 3 ISET X1 X2 VDD ICLK2 Input Clock 1 Phase Selectable CLK VCXO ICLK1 Detector Divider Input Clock 0 Charge ISEL Pump 3 SEL2:0 CHGP VIN GND 4 IDT COMMUNICATIONS CLOCK JITTER ATTENUATOR 1 MK2058-01 REV G 051310MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR VCXO AND SYNTHESIZER Pin Assignment Output Clock Selection Table Input / Output Crystal SEL2 SEL1 SEL0 Range Frequency X1 1 20 X2 0 0 0 3.3 to 8.7 kHz 3072 x ICLK VDD 2 19 GND 0 0 1 0.64 to 1.68 MHz 16 x ICLK VDD 3 18 ISEL 0 1 0 1 to 2.7 MHz 10 x ICLK VDD 4 17 ICLK1 0 1 1 1.7 to 4.5 MHz 6 x ICLK VIN 5 16 ICLK2 M 0 0 5 to 13 kHz 2048 x ICLK M 0 1 6 to 15.75 kHz 1716 x ICLK GND 6 15 SEL0 M 1 0 26 to 70 kHz 384 x ICLK GND 7 14 CLK M 1 1 70 to 210 kHz 128 x ICLK GND 8 13 NC 1 0 0 2.5 to 6.75 MHz 4 x ICLK CHGP 9 12 SEL1 1 0 1 3.4 to 9 MHz 3 x ICLK ISET 10 SEL2 11 1 1 0 5 to 13.5 MHz 2 x ICLK 1 1 1 10 to 27 MHz 1 x ICLK Note: For SEL input pin programming: 20-pin 300 mil SOIC 0 = GND, 1 = VDD, M = Floating Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 X1 Crystal Input. Connect this pin to the specified crystal. 2 VDD Power Power Supply. Connect to +3.3 V. 3 VDD Power Power Supply. Connect to +3.3 V. 4 VDD Power Power Supply. Connect to +3.3 V. 5 VIN Input VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop filter as shown in this data sheet. 6 GND Power Connect to ground. 7 GND Power Connect to ground. 8 GND Power Connect to ground. 9 CHGP Output Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. 10 ISET Charge pump current setting node, connection for setting resistor. 11 SEL2 Input Output Frequency Selection Pin 2. Determines output frequency as per table above. Internally biased to VDD/2. 12 SEL1 Input Output Frequency Selection Pin 1. Determines output frequency as per table above. Internal pull-up resistor. 13 NC Input No Internal Connection. 14 CLK Output Clock Output. 15 SEL0 Input Output Frequency Selection Pin 0. Determines output frequency as per table above. Internal pull-up resistor. 16 ICLK2 Input Input Clock Connection 2. Connect an input reference clock to this pin. If unused, connect to ground. 17 ICLK1 Input Input Clock Connection 1. Connect an input reference clock to this pin. If unused, connect to ground. 18 ISEL Input Input Selection. Used to select which reference input clock is active. Low input level selects ICLK1, high input level selects ICLK2. Internal pull-up resistor. 19 GND Power Connect to ground. 20 X2 Crystal Output. Connect this pin to the specified crystal. IDT COMMUNICATIONS CLOCK JITTER ATTENUATOR 2 MK2058-01 REV G 051310

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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