308RILF Renesas

DATASHEET SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER ICS308 Description Features The ICS308 is a versatile serially programmable, quad Packaged in 20-pin SSOP (QSOP) Pb-free, RoHS PLL clock source. The ICS308 can generate any compliant frequency from 250 kHz to 200 MHz, and up to 6 Operating voltage of 3.3 V different output frequencies simultaneously. The Highly accurate frequency generation outputs can be reprogrammed on the fly, and will lock to a new frequency in 10 ms or less. Smooth transitions M/N Multiplier PLL: M = 1..2048, N = 1..1024 (in which the clock duty cycle remains roughly 50%) are Serially programmable: user determines the output guaranteed if the output divider is not changed. frequency via a 3-wire interface The device includes a PDTS pin which tri-states the Eliminates need for custom quartz oscillators output clocks and powers down the entire chip. Input crystal frequency of 5 - 27 MHz The ICS308 default for non-programmed start-up are Optional programmable on-chip crystal capacitors buffered reference clock outputs on all clock output Output clock frequencies up to 200 MHz pins. Reference clock output Power down tri-state mode Very low jitter Block Diagram 3 VDD CLK1 PLL1 CLK2 STROBE CLK3 Divide SCLK PLL2 CLK4 Logic DATA and CLK5 Output PLL3 CLK6 Enable Crystal or Control clock input CLK7 PLL4 X1/ICLK CLK8 Crystal CLK9 Oscillator X2 GND 2 External capacitors are required with a crystal input. PDTS IDT / ICS SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 1 ICS308 REV L 051310ICS308 SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER Pin Assignment DATA 1 20 STROBE X2 2 19 SCLK X1/ICLK 3 18 PDTS CLK9 4 17 VDD VDD 5 16 VDD GND 6 15 GND CLK1 7 14 CLK5 CLK2 8 13 CLK6 CLK3 9 12 CLK7 CLK4 10 11 CLK8 20 pin (150 mil) SSOP (QSOP) Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 DATA Input Serial data input. 2 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. 4 CLK9 Output Output clock 9. Default of Reference frequency output when unprogrammed. 5 VDD Power Connect to +3.3 V. 6 GND Power Connect to Ground. 7 CLK1 Output Output clock 1. Default of Reference frequency output when unprogrammed. 8 CLK2 Output Output clock 2. Default of Reference frequency output when unprogrammed. 9 CLK3 Output Output clock 3. Default of Reference frequency output when unprogrammed. 10 CLK4 Output Output clock 4. Default of Reference frequency output when unprogrammed. 11 CLK8 Output Output clock 8. Default of Reference frequency output when unprogrammed. 12 CLK7 Output Output clock 7. Default of Reference frequency output when unprogrammed. 13 CLK6 Output Output clock 6. Default of Reference frequency output when unprogrammed. 14 CLK5 Output Output clock 5. Default of Reference frequency output when unprogrammed. 15 GND Power Connect to Ground. 16 VDD Power Connect to +3.3 V. 17 VDD Power Connect to +3.3 V. 18 PDTS Input Powers down entire chip, tri-states all outputs when low. Internal pull-up. 19 SCLK Input Serial Shift register clock. See timing diagram. 20 STROBE Input Strobe to load data. See timing diagram. Use external 250 kOhm pull-up. IDT / ICS SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2 ICS308 REV L 051310