PL902xxx Revision 1.1 General Description Features The PL902xxx series is a low-power, small form-factor, Lowest power and smallest programmable jitter high-performance OTP-based device and a member of attenuator Micrels JitterBlocker, factory programmable jitter Input/output frequency up to 200MHz attenuators. The JitterBlocker product family cleans any I/O pins can be configured as output enable (OE), deterministic jitter, thereby improving the peak-to-peak frequency switching (CSEL), power down (PDB) input, jitter, accumulated jitter, and even the phase noise. The or CLK1(2) output. PL902xxx is capable of reducing thousands of <10A current consumption with PDB active picoseconds of period jitter in a clock to a level below 100ps peak-to-peak, making that clock usable for many Operating temperature range from 40C to +85 C more applications. Available in 6-pin SOT23 GREEN/RoHS-compliant packages. The PL902xxx operates on a single 2.5V or 3.3V supply, consumes little power, and is housed in a small SOT23 Related devices: package for a broad range of applications. Programmable PL903xxx: Single-ended input, differential output, and I/O pins can be configured as output enable (OE), phase noise cleaning. configuration select (CSEL), power down (PDB) input, or PL904xxx: Differential input, two differential outputs, CLK1 (2) output. The power down feature of PL902xxx, and phase noise cleaning when activated, allows the IC to consume less than 10A of power, while its programming flexibility allows filtering of Applications any clock frequency, up to 200MHz. IEEE1588 GPIO clock cleanup Datasheets and support documentation are available on FPGA-generated clock cleanup Micrels web site at: www.micrel.com. 1/10/40/100 Gigabit Ethernet (GbE) SONET/SDH Block Diagram PCI-Express CPRI/OBSAI wireless base stations Fibre Channel SAS/SATA DIMM Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. PL902xxx Ordering Information Part Number Marking Shipping Junction Temp. Range Package PL902xxxUSY TR K2XXX Tape and Reel 40 to +85C SOT23-6L Pin Configuration SOT23-6L (3mm 3mm 1.35mm) Pin Description Pin Number Pin Name Pin Type Pin Level Pin Function PDB, OE, Customizable pin: power down or output enable control 1 I/O LVCMOS CLK1 input with pull-up or clock output. 2 GND GND Power supply ground 3 REF IN I, (SE) LVCMOS Reference clock input 4 VDD PWR Power supply Customizable pin: configuration select control input with 5 CSEL, CLK2 I/O LVCMOS pull-up or clock output. 6 CLK0 O LVCMOS Clock output Key Programming Parameters CLK 0:2 Programmable Output Drive Strength Output Frequency Input/Output CLK0 = REFIN Three optional drive strengths to choose One output pin can be configured as: CLK1 = CLK0 from: OE input CLK2 = CLK0, CLK0/2, or CLK0/4 Low: 4mA PDB input Frequency translation is optional within the Standard: 8mA (default) specified frequency range. CSEL input High: 16mA CLK1, 2 output Revision 1.1 August 1, 2014 2 tcghelp micrel.com or (408) 955-1690