700MHZ, Low Jitter, Crystal-to-3.3V 84329B LVPECL Frequency Synthesizer DATA SHEET General Description Features The 84329B is a general purpose, single output high frequency Fully integrated PLL, no external loop filter requirements synthesizer.TheVCO operates at a frequency range of 250MHz to One differential 3.3V LVPECL output 700MHz.TheVCO frequency is programmed in steps equal to the Parallel resonant crystal oscillator interface value of the crystal frequency divided by 16.TheVCO and output Output frequency range: 31.25MHz 700MHz frequency can be programmed using the serial or parallel interfaces to the configuration logic.The output can be configured to divide the VCO range: 250MHz 700MHz VCOfrequencyby1,2,4,and8.Outputfrequencystepsassmallas Parallel interface for programming counter and output dividers 125kHz to 1MHz can be achieved using a 16MHz crystal depending during power-up on the output dividers. Serial 3 wire interface RMS period jitter: 5.5ps (maximum) Cycle-to-cycle jitter: 35ps (maximum) 3.3V supply voltage 0C to 70C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignments OE XTAL IN OSC 32 31 30 29 28 27 26 25 XTAL OUT 1 S CLOCK 24 nc S DATA 2 23 N1 84329B 16 S LOAD 3 N0 32-Lead LQFP 22 7mm x 7mm x 1.4mm M8 VCCA 4 21 PLL package body VCCA M7 5 20 PHASEDETECTOR Y Package 1 nc 6 M6 19 2 1 TopView 4 FOUT nc VCO 7 M5 18 8 nFOUT 0 M XTAL IN 8 M4 17 910 11 1213 14 15 16 S LOAD CONFIGURATION S DATA TEST INTERFACE S CLOCK LOGIC nP LOAD M0:M8 N0:N1 84329B REVISION B 07/29/14 1 2014 Integrated Device Technology, Inc. XTAL OUT VCC OE FOUT nP LOAD nFOUT M0 VEE VCC M1 M2 VCC M3 TEST nc VEE84329B DATA SHEET Functional Description NOTE: The functional description that follows describes operation directly to the M divider and N output divider. On the LOW-to-HIGH using a 16MHz crystal. Valid PLL loop divider values for different transitionofthenP LOADinput,thedataislatchedandtheMdivider crystal or input frequencies are defined in the Input Frequency remains loaded until the next LOW transition on nP LOAD or until a Characteristics, Table 6, NOTE 1. serial event occurs.TheTEST output is Mode 000 (shift register out) when operating in the parallel input mode.The relationship between The84329BfeaturesafullyintegratedPLLandthereforerequiresno theVCOfrequency,thecrystalfrequencyandtheMdividerisdefined external components for setting the loop bandwidth. A as follows: series-resonant, fundamental crystal is used as the input to the fVCO = fXTAL x M on-chip oscillator.The output of the oscillator is divided by 16 prior to 16 the phase detector. With a 16MHz crystal, this provides a 1MHz The M value and the required values of M0 through M8 are shown in reference frequency.TheVCO of the PLL operates over a range of Table 3B, ProgrammableVCO Frequency FunctionTable.Valid M 250MHzto700MHz.TheoutputoftheMdividerisalsoappliedtothe values for which the PLL will achieve lock are defined as 250 M phase detector. 511.The frequency out is defined as follows: The phase detector and the M divider force theVCO output fre- fout = fVCO = fXTAL x M quency to be M times the reference frequency by adjusting theVCO N16 N control voltage. Note that for some values of M (either too high or too Serial operation occurs when nP LOAD is HIGH and S LOAD is low), the PLL will not achieve lock.The output of theVCO is scaled LOW.The shift register is loaded by sampling the S DATA bits with by a divider prior to being sent to each of the LVPECL output buffers. the rising edge of S CLOCK.The contents of the shift register are loaded into the M divider when S LOAD transitions from The divider provides a 50% output duty cycle. LOW-to-HIGH.The M divide and N output divide values are latched The programmable features of the 84329B support two input modes ontheHIGH-to-LOWtransitionofS LOAD.IfS LOADisheldHIGH, to program the M divider and N output divider.The two input data at the S DATA input is passed directly to the M divider on each operational modes are parallel and serial. Figure 1 shows the timing rising edge of S CLOCK.The serial mode can be used to program diagramforeachmode.InparallelmodethenP LOADinputisLOW. the M and N bits and test bitsT2:T0.The internal registersT2:T0 determine the state of theTEST output as follows: The data on inputs M0 through M8 and N0 through N1 is passed T2 T1 T0 TEST Output f OUT 0 0 0 Shift Register Out f OUT 0 0 1 HIGH f OUT 0 1 0 PLL Reference XTAL 16 f OUT 0 1 1 (VCO M) (non 50% Duty Cycle M Divider) f OUT 100 f , LVCMOS Output Frequency < 200MHz f OUT OUT 1 0 1 LOW f OUT 1 1 0 S CLOCK M (non 50% Duty Cycle M Divider) S CLOCK N Divider 111 f 4 f OUT OUT SERIAL LOADING S CLOCK T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S DATA t t S H S LOAD t nP LOAD S PARALLEL LOADING M, N M0:M8, N0:N1 nP LOAD t t S H nP LOAD Time Figure 1. Parallel & Serial Load Operations REVISION B 07/29/14 2 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER