ZL30256 3-Channel, 10-Input, 18-Output General-Purpose Jitter Attenuator Data Sheet Block Diagram page 7. Register Map section 9.3 October 2020 Features Ordering Information One, Two or Three DPLL Channels ZL30256LFG7 80-lead LGA Trays Programmable bandwidth, 14Hz to 470Hz NiAu (Pb-free) Freerun or holdover on loss of all inputs Package size: 11 x 11 mm Hitless reference switching -40 C to +85 C High-resolution holdover averaging Per-DPLL phase adjustment, 1ps resolution Programmable tracking range, phase-slope Precise output alignment circuitry and per- limiting, frequency-change limiting and other output phase adjustment advanced features Per-output enable/disable and glitchless Input Clocks start/stop (stop high or low) Accepts up to 10 differential or CMOS inputs Local Oscillator Any input frequency from 1kHz to 900MHz Operates from a single low-cost XO: 23.75- Per-input activity and frequency monitoring 25MHz, 47.5-50MHz, 114.285-125MHz Automatic or manual reference switching General Features Revertive or nonrevertive switching Automatic self-configuration at power-up from Input-input phase measurement, 1ps resolution internal Flash memory Input-DPLL phase measurement, 1ps resolution Input-to-output alignment <200ps (ext feedback) Per-input phase adjustment, 1ps resolution Internal compensation (1ppt) for local oscillator frequency error in DPLLs and input monitors Output Clock Frequency Generation Numerically controlled oscillator behavior in Any output frequency from 1Hz to 1045MHz each DPLL and each fractional output divider (180MHz max for Synth0) Easy-to-configure design requires no external High-resolution fractional frequency conversion VCXO or loop filter components with 0ppm error 7 GPIO pins with many possible behaviors Synthesizers 1 & 2 have integer and fractional 2 dividers to make a total of 5 frequency families SPI or I C processor Interface Output jitter from Synth 1 & 2 is <0.3ps RMS 1.8V and 3.3V core VDD voltages Output jitter from fractional dividers is typically Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out < 1ps RMS, many frequencies <0.5ps RMS Easy-to-use evaluation/programming software Each HPOUTP/N pair can be LVDS, LVPECL, HCSL, 2xCMOS, HSTL or programmable diff. Applications Jitter attenuation, frequency conversion, and In 2xCMOS mode, the P and N pins can be frequency synthesis in a wide variety of different frequencies (e.g. 125MHz and 25MHz) system types Four output banks each with VDDO pin CMOS output voltages from 1.5V to 3.3V Per-synthesizer phase adjust, 1ps resolution Per-output programmable duty cycle 1 Microsemi Confidential Copyright 2020. Microsemi Corporation. All Rights Reserved. ZL30256 Data Sheet Table of Contents 1. BLOCK DIAGRAM ........................................................................................................................ 7 2. APPLICATION EXAMPLE ............................................................................................................ 7 3. DETAILED FEATURES ................................................................................................................. 8 3.1 INPUT BLOCK FEATURES ............................................................................................................... 8 3.2 DPLL FEATURES .......................................................................................................................... 8 3.3 SYNTHESIZER FEATURES .............................................................................................................. 8 3.4 LOW-JITTER OUTPUT CLOCK FEATURES ........................................................................................ 8 3.5 GENERAL-PURPOSE OUTPUT CLOCK FEATURES ............................................................................ 9 3.6 LOCAL OSCILLATOR ...................................................................................................................... 9 3.7 GENERAL FEATURES .................................................................................................................... 9 3.8 EVALUATION SOFTWARE ............................................................................................................... 9 4. PIN DIAGRAM ............................................................................................................................. 10 5. PIN DESCRIPTIONS ................................................................................................................... 11 6. FUNCTIONAL DESCRIPTION .................................................................................................... 14 6.1 INPUT REFERENCES ................................................................................................................... 14 6.1.1 Input Sources ....................................................................................................................................... 14 6.1.2 Input Reference Monitoring .................................................................................................................. 14 6.1.3 Input Gapped Clocks ............................................................................................................................ 18 6.1.4 Input Buffers ......................................................................................................................................... 18 6.1.5 Input-to-Input Phase Offset Measurement ........................................................................................... 21 6.1.6 Input-to-DPLL Phase Offset Measurement .......................................................................................... 22 6.1.7 Input Phase Adjustment ....................................................................................................................... 22 6.2 INPUT-OUTPUT SPECIAL FORMATS .............................................................................................. 23 6.2.1 Input-Output Reference-Sync Pair ....................................................................................................... 23 6.3 DIGITAL PHASE LOCKED LOOP (DPLL) ........................................................................................ 24 6.3.1 DPLL Input Monitoring Masks .............................................................................................................. 24 6.3.2 DPLL Input Reference Priority ............................................................................................................. 24 6.3.3 DPLL Input Pull-In, Hold-In Range ....................................................................................................... 24 6.3.4 DPLL Input Tolerance Criteria ............................................................................................................. 25 6.3.5 DPLL Input Advance and Delay ........................................................................................................... 25 6.3.6 DPLL Phase Slope Limiter ................................................................................................................... 25 6.3.7 DPLL Core Modes ................................................................................................................................ 25 6.3.8 DPLL Status Indicators ........................................................................................................................ 26 6.3.9 DPLL Bandwidth (Jitter/Wander Transfer) ........................................................................................... 26 6.3.10 DPLL Programmable Damping ............................................................................................................ 26 6.3.11 DPLL Lock Time and Fast Lock Methods ............................................................................................ 26 6.3.12 DPLL Hitless Reference Switching ...................................................................................................... 26 6.3.13 DPLL Holdover Capability .................................................................................................................... 27 6.3.14 DPLL Output Frequency Offset and Master Clock Frequency Adjustment ......................................... 29 6.3.15 DPLL Supervision & Management ....................................................................................................... 29 6.3.16 DPLL Jitter/Wander Generation ........................................................................................................... 31 6.3.17 DPLL Frequency and Phase Reporting ............................................................................................... 31 6.4 INPUT-OUTPUT CONVERSION ...................................................................................................... 31 6.4.1 Input-to-Output and Output-to-Output Phase Alignment ..................................................................... 31 6.4.2 Rate Conversion Function and FEC Support ...................................................................................... 32 6.4.3 Mapping DPLLs to Synthesizers .......................................................................................................... 33 6.5 OUTPUT FREQUENCY SYNTHESIZERS .......................................................................................... 33 6.5.1 Synth0 Frequency Offset ..................................................................................................................... 34 6.5.2 Synth1 and Synth2 Fractional Dividers ................................................................................................ 34 2 Microsemi Confidential