ADC0808S125HW/C1,1

ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Rev. 03 24 February 2009 Product data sheet 1. General description The ADC0808S is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC) optimized for telecommunication transmission control systems and tape drive applications. It allows signal sampling frequencies up to 250 MHz. The ADC0808S clock inputs are selectable between 1.8 V Complementary Metal Oxide Semiconductor (CMOS) or Low-Voltage Differential Signals (LVDS). The data output signal levels are 1.8 V CMOS. All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and DEL1) are 1.8 V CMOS compatible. The ADC0808S offers the most exible acquisition control system possible due to its programmable Complete Conversion Signal (CCS) which allows the delay time of the acquisition clock and acquisition clock frequency to be adjusted. The ADC0808S is supplied in an HTQFP48 package. 2. Features n 8-bit resolution n High-speed sampling rate up to 250 MHz n Maximum analog input frequency up to 560 MHz n Programmable acquisition output clock (complete conversion signal) n Differential analog input n Integrated voltage regulator or external control for analog input full-scale n Integrated voltage regulator for input common-mode reference n Selectable 1.8 V CMOS or LVDS clock input n 1.8 V CMOS digital outputs n 1.8 V CMOS compatible static digital inputs n Binary or 2s complement CMOS outputs n Only 2 clock cycles latency n Industrial temperature range from - 40 Cto+85 C n HTQFP48 package 3. Applications n 2.5G and 3G cellular base infrastructure radio transceivers n Wireless access systems n Fixed telecommunicationsADC0808S125/250 NXP Semiconductors Single 8-bit ADC, up to 125 MHz or 250 MHz n Optical networking n Wireless Local Area Network (WLAN) infrastructure n Tape drive applications 4. Ordering information Table 1. Ordering information Type number Sampling frequency Package (MHz) Name Description Version ADC0808S125HW/C1 125 HTQFP48 plastic thermal enhanced thin quad at package; SOT545-2 48 leads; body 7 7 1 mm; exposed die pad ADC0808S250HW/C1 250 5. Block diagram CLKSEL CLK+ CLK- 36 37 38 39 DEL0 CLOCK DRIVER 40 DEL1 17 CCS LATCH ADC0808S 26 CCSSEL 33 8 8 IN TRACK LATCH D0 to D7 RESISTOR ADC AND 32 LADDERS CORE 21 INN HOLD OTC 30 FSIN/ 20 U/I IR LATCH REFSEL INTERNAL CMADC OUTPUTS REFERENCE REFERENCE ENABLE 29 19 001aai267 CMADC CE_N Fig 1. Block diagram ADC0808S125_ADC0808S250_3 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 24 February 2009 2 of 23