2 O/P 1.5V PCIe Gen1-2-3 Clock Generator 9FGU0231 DATASHEET Description Features/Benefits The 9FGU0231 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 4 resistors compared to standard PCIe clock family. The device has 2output enables for clock PCIe devices management, 2 different spread spectrum levels in addition to 23mW typical power consumption reduced thermal spread off and 2 selectable SMBus addresses. concerns OE pins support DIF power management Recommended Application Programmable Slew rate for each output allows tuning for various line lengths 1.5V PCIe Gen1-2-3 clock generator Programmable output amplitude allows tuning for various application environments Output Features DIF outputs blocked until PLL is locked clean system 2 - 100MHz Low-Power (LP) HCSL DIF pairs start-up 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) Selectable 0%, -0.25% or -0.5% spread on DIF outputs support reduces EMI External 25MHz crystal supports tight ppm with 0 ppm synthesis error Key Specifications Configuration can be accomplished with strapping pins DIF cycle-to-cycle jitter <50ps SMBus interface not required for device control DIF output-to-output skew <50ps Selectable SMBus addresses multiple devices can easily DIF phase jitter is PCIe Gen1-2-3 compliant share an SMBus segment REF phase jitter is < 3.0ps RMS 3.3V tolerant SMBus interface works with legacy controllers Space saving 24-pin 4x4 mm VFQFPN minimal board space Block Diagram XIN/CLKIN 25 REF1.5 OSC X2 vOE(1:0) DIF1 SS Capable PLL DIF0 vSADR vSS EN tri CKPWRGD PD CONTROL LOGIC SDATA 3.3 SCLK 3.3 9FGU0231 OCTOBER 18, 2016 1 2016 Integrated Device Technology, Inc.9FGU0231 DATASHEET Pin Configuration 24 23 22 21 20 19 XIN/CLKIN 25 1 18 DIF1 X2 2 17 DIF1 VDDXTAL1.5 3 VDDA1.5 16 9FGU0231 vSADR/REF1.5 4 GNDA 15 GNDREF 5 DIF0 14 GNDDIG 613DIF0 78 9 101112 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table SADR Address + Read/Write Bit State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx CKPWRGD PD REF OE bit True O/P Comp. O/P 1 0 X Low Low Hi-Z 1 1 Running Running Running 1 0 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 35,24 XTAL, REF 76 Digital 11,20 10,21 DIF outputs 16 15 PLL Analog 2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR 2 OCTOBER 18, 2016 VDDDIG1.5 GNDXTAL SCLK 3.3 vSS EN tri SDATA 3.3 CKPWRGD PD GND GND VDD1.5 VDD1.5 vOE0 vOE1