6 O/P 1.5V PCIe Gen1-2-3 Clock Generator 9FGU0641 w/Zo=100ohms DATASHEET Description Features/Benefits The 9FGU0641 is a member of IDT s 1.5V Ultra-Low-Power Direct connection to 100ohm transmission lines saves 24 PCIe clock family with integrated output terminations resistors compared to standard PCIe device providing Zo=100ohms. The device has 6 output enables for 45mW typical power consumption reduced thermal clock management and supports 2 different spread spectrum concerns levels in addition to spread off. Outputs can optionally be supplied from any voltage between 1.05 and 1.5V maximum power savings Recommended Application OE pins support DIF power management Programmable Slew rate for each output allows tuning for 1.5V PCIe Gen1-2-3 clock generator various line lengths Programmable output amplitude allows tuning for various Output Features application environments 6 -100MHz Low-power HCSL (LP-HCSL) DIF pairs DIF outputs blocked until PLL is locked clean system w/Zo=100 start-up 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) Selectable 0%, -0.25% or -0.5% spread on DIF outputs support reduces EMI External 25MHz crystal supports tight ppm with 0 ppm Key Specifications synthesis error Configuration can be accomplished with strapping pins DIF cycle-to-cycle jitter <50ps SMBus interface not required for device control DIF output-to-output skew <60ps Selectable SMBus addresses multiple devices can easily DIF phase jitter is PCIe Gen1-2-3 compliant share an SMBus segment REF phase jitter is < 3.0ps RMS 3.3V tolerant SMBus interface works with legacy controllers Space saving 40-pin 5x5 mm VFQFPN minimal board space Block Diagram X1 25 REF1.8 X2 OSC vOE(5:0) 6 DIF5 DIF4 SS Capable PLL DIF3 vSADR DIF2 vSS EN tri CONTROL DIF1 CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 DIF0 9FGU0641 OCTOBER 18, 2016 1 2016 Integrated Device Technology, Inc.9FGU0641 DATASHEET Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSS EN tri130 vOE3 X1 25229 DIF3 X2328 DIF3 VDDXTAL1.5 VDDIO 427 9FGU0641 VDDREF1.5526 VDDA1.5 vSADR/REF1.5 NC 625 Paddle is GND NC724 vOE2 GNDDIG DIF2 823 SCLK 3.3922 DIF2 SDATA 3.3 10 21 vOE1 11 12 13 14 15 16 17 18 19 20 40-pin VFQFPN, 5x5 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write Bit SADR Address x State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 Power Management Table SMBus DIFx CKPWRGD PD REF OE bit OEx True O/P Comp. O/P 1 0 X X Low Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD VDDIO GND 441 XTAL OSC 5 41 REF Power Digital (dirty) 11 8 Power 12,17,27,32,39 41 DIF outputs 26 41 PLL Analog 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 2 OCTOBER 18, 2016 VDDDIG1.5 CKPWRGD PD VDDIO VDDIO vOE0 vOE5 DIF0 DIF5 DIF0 DIF5 VDD1.5 vOE4 VDDIO DIF4 DIF1 DIF4 DIF1 VDDIO NC VDD1.5