TSM6963SD 20V Dual P-Channel MOSFET Pin Definition: TSSOP-8 PRODUCT S UMMARY 1. Drain 1 8. Drain 2 V (V) R (m) I (A) 2. Source 1 7. Source 2 DS DS(on) D 3. Source 1 6. Source 2 30 V = -4.5V -4.5 GS 4. Gate 1 5. Gate 2 -20 42 V = -2.5V -3 GS 68 V = -1.8V -2 GS Block Diagram Features Advance Trench Process Technology High Density Cell Design for Ultra Low On-resistance Application Load Switch PA Switch Ordering Information Part No. Package Packing TSM6963SDCA RVG TSSOP-8 3Kpcs / 13 Reel Dual P-Channel MOSFET Note: G denote for Halogen Free Product Absolute Maximum Rating (Ta = 25C unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage V -20 V DS Gate-Source Voltage V 12 V GS Continuous Drain Current, V 4.5V. I -4.5 A GS D Pulsed Drain Current, V 4.5V I -16 A GS DM a,b Continuous Source Current (Diode Conduction) I -1.0 A S Ta = 25C 1.14 Maximum Power Dissipation P W D Ta = 70C 0.73 Operating Junction Temperature T +150 C J Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG Thermal Performance Parameter Symbol Limit Unit Junction to Foot (Drain) Thermal Resistance R 75 C/W JF Junction to Ambient Thermal Resistance (PCB mounted) R 90 C/W JA Notes: a. Surface Mounted on 1 x 1 FR4 Board. b. Pulse width limited by maximum junction temperature Document Number: DS P0000129 1 Version: D15 TSM6963SD 20V Dual P-Channel MOSFET Electrical Specifications (Ta =25C unless otherwise noted) Parameter Conditions Symbol Min Typ Max Unit Static Drain-Source Breakdown Voltage V =0V, I =-250uA BV -20 -- -- V GS D DSS Gate Threshold Voltage V =V , I =-250uA V -0.5 -0.7 -1.0 V DS GS D GS(TH) Zero Gate Voltage Drain Current V =-16V, V =0V I -- -- -1 uA DS GS DSS Gate Body Leakage V =12V, V =0V I -- -- 100 nA GS DS GSS On-State Drain Current V =-5V, V =-4.5V I -25 -- -- A DS GS D(ON) V =-4.5V, I =-4.5A -- 23 30 GS D Drain-Source On-State Resistance V =-2.5V, I =-3A R -- 30 42 m GS D DS(ON) V =-1.8V, I =-2A -- 45 68 GS D Forward Transconductance V =-5V, I =-4.5A g -- 16 -- S DS D fs Diode Forward Voltage I =-0.5A, V =0V V -- - 0.8 -1.3 V S GS SD b Dynamic Total Gate Charge Q -- 14 20 g V =-10V, I =-4.5A, DS D nC Gate-Source Charge Q -- 2.1 10 gs V =-4.5V GS Gate-Drain Charge Q -- 4.7 -- gd Input Capacitance C -- 1500 -- iss V =-10V, V =0V, DS GS pF Output Capacitance C -- 220 -- oss f =1.0MHz Reverse Transfer Capacitance C -- 160 -- rss b,C Switching Turn-On Delay Time t -- 6 11 d(on) V =-10V, R =10, DD L Turn-On Rise Time t -- 13 23 r I =-1A, V =-4.5V, nS D GEN Turn-Off Delay Time t -- 86 145 d(off) R =6 G Turn-Off Fall Time t -- 42 70 f Notes: a. pulse test: PW 300S, duty cycle 2% b. For DESIGN AID ONLY, not subject to production testing. c. Switching time is essentially independent of operating temperature. Document Number: DS P0000129 2 Version: D15