TC74VHCT373AFT(SPL Toshiba

TC74VHCT373AF/AFT/AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT373AF, TC74VHCT373AFT, TC74VHCT373AFK Octal D-Type Latch with 3-State Output The TC74VHCT373A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate TC74VHCT373AF 2 C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 TC74VHCT373AFT V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can (Note) be applied to the input and output pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. Note: Output in off-state Features TC74VHCT373AFK High speed: t = 7.7 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Compatible with TTL inputs: V = 0.8 V (max) IL V = 2.0 V (min) IH Power down protection is provided on all inputs and outputs. Balanced propagation delays: t t pLH pHL Low noise: V = 1.5 V (max) OLP Pin and function compatible with the 74 series Weight (74AC/HC/F/ALS/LS etc.) 373 type. SOP20-P-300-1.27A: 0.22 g (typ.) TSSOP20-P-0044-0.65A: 0.08 g (typ.) VSSOP20-P-0030-0.50: 0.03 g (typ.) Start of commercial production 1995-12 1 2014-03-01 TC74VHCT373AF/AFT/AFK Pin Assignment IEC Logic Symbol (1) OE EN 1 20 V OE CC (11) LE C1 Q0 2 19 Q7 (3) (2) D0 1D Q0 D0 18 D7 3 (4) (5) D1 Q1 (7) (6) D1 4 17 D6 D2 Q2 (8) (9) D3 Q3 Q1 5 16 Q6 (13) (12) D4 Q4 (14) (15) D5 Q5 Q2 6 15 Q5 (17) (16) D6 Q6 (18) (19) D2 7 14 D5 D7 Q7 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 LE (top view) Truth Table Inputs Output OE LE D H X X Z L L X Qn L H L L L H H H X: Dont care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level. System Diagram D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 D D D D DD D D D L Q L Q L Q L Q L Q L Q L Q L Q 11 LE 1 OE 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 2014-03-01