Product Information

W29N02GVBIAA

W29N02GVBIAA electronic component of Winbond

Datasheet
NAND Flash Serial 3V 2G-bit 256M x 8 25ns
Manufacturer: Winbond
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

3: USD 3.9005 ea
Line Total: USD 11.7

0 - Global Stock
MOQ: 3  Multiples: 3
Pack Size: 3

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 210
Multiples : 1

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W29N02GVBIAA
Winbond

210 : USD 6.1228
250 : USD 6.0624
500 : USD 6.0007
1000 : USD 5.9417
2000 : USD 5.8813
2500 : USD 5.8236
3000 : USD 5.7645
4000 : USD 5.7067
5000 : USD 5.6503
10000 : USD 5.5939

0 - WHS 2


Ships to you between Tue. 14 May to Thu. 16 May

MOQ : 210
Multiples : 210

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W29N02GVBIAA
Winbond

210 : USD 4.6489
420 : USD 4.6248

0 - WHS 3


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 3
Multiples : 3

Stock Image

W29N02GVBIAA
Winbond

3 : USD 3.9005
10 : USD 3.3308
25 : USD 3.2776
50 : USD 3.1271
100 : USD 2.9496
250 : USD 2.8906

0 - WHS 4


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 3
Multiples : 3

Stock Image

W29N02GVBIAA
Winbond

3 : USD 3.9005
10 : USD 3.3308
25 : USD 3.2776
50 : USD 3.1271
100 : USD 2.9496
250 : USD 2.8906

Read More Specifications

     
Manufacturer
Product Category
Interface Type
Organisation
Timing Type
Data Bus Width
Supply Voltage - Min
Supply Voltage - Max
Supply Current - Max
Minimum Operating Temperature
Maximum Operating Temperature
Programmable
Boot Type
Cell Type
Address Bus
Operating Temp Range
Program/Erase Volt Typ
Density
Rad Hardened
Operating Temperature Classification
Access Time Max
Operating Supply Voltage Typ
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Additional Infomation About Product

W29N02GV W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY th Release Date: December 4 , 2017 1 Revision C W29N02GV Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................ 7 2. FEATURES .................................................................................................................................... 7 3. PACKAGE TYPES AND PIN CONFIGURATIONS ....................................................................... 8 3.1 Pin assignment 48-pin TSOP1(x8) ....................................................................................... 8 3.2 Pin assignment 63 ball VFBGA (x8) ..................................................................................... 9 3.3 Pin Descriptions .................................................................................................................. 10 4. PIN DESCRITPIONS ................................................................................................................... 11 4.1 Chip Enable ( CE) .............................................................................................................. 11 4.2 Write Enable ( WE) ............................................................................................................ 11 4.3 Read Enable ( RE) ............................................................................................................. 11 4.4 Address Latch Enable (ALE) .............................................................................................. 11 4.5 Command Latch Enable (CLE) ........................................................................................... 11 4.6 Write Protect ( WP) ............................................................................................................ 11 4.7 Ready/Busy (RY/ BY) ........................................................................................................ 11 4.8 Input and Output (I/Ox) ....................................................................................................... 11 5. BLOCK DIAGRAM ....................................................................................................................... 12 6. MEMORY ARRAY ORGANIZATION ........................................................................................... 13 6.1 Array Organization (x8) ....................................................................................................... 13 7. MODE SELECTION TABLE ........................................................................................................ 14 8. COMMAND TABLE ...................................................................................................................... 15 9. DEVICE OPERATIONS ............................................................................................................... 17 9.1 READ operation .................................................................................................................. 17 9.1.1 PAGE READ (00h-30h) ........................................................................................................ 17 9.1.2 CACHE READ OPERATIONS .............................................................................................. 17 9.1.3 TWO PLANE READ (00h-00h-30h) ...................................................................................... 21 9.1.4 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 23 9.1.5 READ ID (90h) ...................................................................................................................... 25 9.1.6 READ PARAMETER PAGE (ECh) ....................................................................................... 26 9.1.7 READ STATUS (70h) ........................................................................................................... 28 9.1.8 READ STATUS ENHANCED (78h) ...................................................................................... 30 9.1.9 READ UNIQUE ID (EDh) ...................................................................................................... 31 9.2 PROGRAM operation ......................................................................................................... 32 9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 32 9.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 32 9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 33 9.2.4 CACHE PROGRAM (80h-15h) ............................................................................................. 33 9.2.5 TWO PLANE PAGE PROGRAM .......................................................................................... 35 9.3 COPY BACK operation ....................................................................................................... 38 9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 38 9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 38 9.3.3 TWO PLANE READ for COPY BACK ................................................................................... 39 9.3.4 TWO PLANE PROGRAM for COPY BACK .......................................................................... 39 9.4 BLOCK ERASE operation .................................................................................................. 43 th Release Date: December 4 , 2017 2 Revision C

HS Compliance

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)

Winbond may also be referenced as

Winbond Elec
WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA

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