Application Note 18 Issue 1 March 1996 Power MOSFET Gate Driver Circuits using High Current Super- Transistors 6A Pulse Rated SOT23 Transistors for High Frequency MOSFET Interfacing Neil Chadderton The power MOSFET is commonly (thus limiting the operating frequency presented and regarded as a voltage and increasing the time spent in the driven device, and as such there is a linear region thereby producing high natural expectation that it can be driven switching losses), or the R element from any pulse source, irrespective of must be minimised. that sources energy, or current capability. As a guide, the input capacitance of power MOSFETs ranges from a few This assumption is partly justified, if the hundred picofarads to tens of system in question only pulses or nanofarads. This capacitance is switches the MOSFET at a low increased by the effective amplification frequency, or in pure DC circuits, where of the drain-gate capacitance by the the transistor may only be used in a voltage gain of the circuit (Miller effect), toggled state. However, for typical such that the apparent capacitive switching frequencies from several kHz component of the CR network assumes upwards, attention must be paid to the a value of 2 to 5 times the value of the gate drive requirements to ensure datasheet stated C . As this iss efficient and saturated switching of amplification effect is so circuit/bias the MOSFET. This must be considered as condition dependent, a useful tool has the gate-source (g-s) circuit is, to a first been developed that considers the approximation, essentially a CR amount of gate charge required to meet network comprising the g-s a certain condition. Figure 1 shows a capacitance, and the resistance of the chart illustrating the gate charge metallic/silicon interconnects. To this required to switch the ZVN4306A (a network must be added the effective 220m, 1A continuous TO92 part), and resistance, or source impedance of the this parameters dependence on the gate driver circuitry, and for true Miller effect as the drain voltage assessments, consideration of the increases. drain-gate (d-g) capacitance and the Miller effect. Due to this network, the g-s As the operating frequency of switched voltage follows an exponential curve as mode power supplies increases, due to the C elements charge, and so, either the need for less weight and product sufficient time must be given to allow volume demands smaller inductors and this voltage to reach its target value capacitors, the MOSFETs required gate AN18 - 1VGS-Gate Source Voltage (Volts) Application Note 18 Application Note 18 Issue 1 March 1996 Issue 1 March 1996 VDD= also. 16 20V 40V 14 ID=3A 60V R1 Q2 It is necessary therefore, that the gate 12 driver circuitry acts as a low impedance 10 voltage source, to enable the gate Q1 D1 Q4 8 R2 Q4 capacitance to be charged and C1 6 R2 discharged as quickly as possible. It Q3 4 V(logic) must also have the capability of sourcing R1 R3 Q2 Logic 2 and sinking high transient gate currents 0 - possibly several amps, in tens of Q1 0 12 3 4 5 6 78 9 10 11 12 Logic nanoseconds. Standard logic family Q-Charge (nC) gates, and even the output stages of Gate charge v gate-source voltage switch mode controller ICs are rarely able to provide this requirement and so Figure1 Figure 3 Figure 4 would be unable to drive power Gate Charge Curves for the ZVN4306A a Complimentary Emitter Follower Gate Level Shifted PMOS Gate Driver. MOSFETs in many applications. To 1A DC rated 220m E-Line (TO92) Style Driver. provide an interface between the MOSFET. and Figure 5 a method of maintaining logic/PWM and the MOSFET, a high the correct drive level and drive phase, a high current capability (eg significant speed, high current capable (though not voltage must be driven to its final value when deriving a control signal from a 5V current gain at high collector currents), necessarily high power) buffer is in as short a period as possible (within logic based controller, by driving the high F (as a benchmark to a fast T therefore required. EMI constraints) to minimise switching emitter of a fast switching pre-driver switching capability), and ideally high losses. For a given value of required gate transistor. This can either be a ZTX314 gain. As the driver transistors only The gate drive requirement is met by the charge, this means that the current for a through-hole design, or a supply current while the capacitance is complimentary emitter follower circuit capability of the gate drive circuitry must FMMT2369A for a surface mount charging or discharging, the power shown in Figure 2, which should be be carefully considered. version. capability (essentially determined by the constructed with transistors possessing package characteristics) is quite low, As examples of the current required Other variations have been devised and can be tolerated by the smaller +V from the driver stage, and using the gate through-hole and surface mount charge curves as a source: packages. +12V +5V i) A typical 100V, 300m TO220 power Q1 1K By adjusting the amount of resistance in FMMT 618 MOSFET requires approximately 8nC, the charge path as shown, it is possible which for a switching time of say 20ns, 2K2 to delay the turn-on time. This may be R1 FMMT 0* leads to a current requirement of 400mA. necessary in some instances to prevent 2369 0R - see text IRF830 cross-conduction in push-pull output PWM Controller Logic/PWM ii) A typical 500V, 900m TO220 power Drive O/P stages, or to decrease dV/dT to ensure FMMT opto-coup MOSFET needs around 30nC, which 2K2 22pF 718 compliance with EMI/RFI regulations. 0V could lead to a current requirement of 1.5A. ( * Set turn-on delay ) Q2 This basic circuit can be adapted for different circuit topologies and 0V Obviously, paralleled MOSFETs are performance requirements as shown in another concern, but a high current Figure 5 Figures 3, 4 and 5. Figure 3 shows source could be used with the Figure 2 Complimentary Emitter Follower Gate another method of introducing unequal appropriate shared gate drive to reduce Complimentary Emitter Follower Gate Driver using Emitter Driven Switching turn-on/turn-off times Figure 4 shows a component count in this application Driver. Transistor to Retain Phasing. level shifted driver for a PMOS device AN18 - 2 AN18 - 3