Product Information


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Clock Synthesizer/Jitter Cleaner PLL Clock Multiplier
Manufacturer: Diodes Incorporated

Price (USD)

1: USD 2.4255 ea
Line Total: USD 2.4255

7 - Global Stock
Ships to you between
Mon. 10 Apr to Wed. 12 Apr
MOQ: 1 Multiples:1
Pack Size :   1
Availability Price Quantity
7 - Global Stock

Ships to you between Mon. 10 Apr to Wed. 12 Apr

MOQ : 1
Multiples : 1

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Diodes Incorporated

1 : USD 2.4255
10 : USD 1.6875
100 : USD 1.235
500 : USD 1.0488
1000 : USD 0.8913
2500 : USD 0.8637
5000 : USD 0.8388
10000 : USD 0.8125
25000 : USD 0.7888

Diodes Incorporated
Product Category
Clock Synthesizer/Jitter Cleaner
Package / Case
SOIC - 8
Diodes Incorporated
Factory Pack Quantity :
Hts Code
Product Type
Clock Generators
Clock Timer Ics
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PT7C4511 PLL Clock Multiplier Features Description The PT7C4511 is a high performance frequency Zero ppm multiplication error multiplier, which integrates Analog Phase Lock Loop Input crystal frequency of 5 - 30 MHz techniques. Input clock frequency of 1 - 50 MHz The PT7C4511 is the most cost effective way to Output clock frequencies up to 200 MHz generate a high quality, high frequency clock output Peak to Peak Jitter less than 200ps over 200ns from a lower frequency crystal or clock input. It is interval (100~200MHz) designed to replace crystal oscillators in most electronic Low period jitter 50ps (100~200MHz) systems, clock multiplier and frequency translation. 9 selectable frequencies controlled by S0, S1 pins Using Phase-Locked-Loop (PLL) techniques, the device Operating voltages of 3.0 to 5.5V uses a standard fundamental mode, inexpensive crystal Tri-state output for board level testing to produce output clocks up to 200 MHz. Lead free SOIC-8 package The complex Logic divider is the ability to generate nine different popular multiplication factors, allowing one Pin Configuration chip to output many common frequencies. The device also has an Output Enable pin that tri-states 1 8 X1/ICLK X2 the clock output when the OE pin is taken low. This 2 Vcc OE 7 product is intended for clock generation and frequency 3 6 GND S0 translation with low output jitter (variation in the output 4 S1 CLK 5 period). SOIC-8 package Pin Description Clock Output Table Name Pin No. Type Description S1 S0 CLK X1/ICLK 1 X1 Crystal connection or clock input. 0 0 4 0 M (16/3) Vcc 2 P Connect to +3.3V or +5V. 0 1 5 GND 3 P Connect to ground. M 0 2.5 Multiplier select pin, connect to M M 2 S1 4 T1 GND or Vcc or floating (no connection). M 1 (10/3) CLK 5 O Clock output per Table below. 1 0 6 Multiplier select pin 0, connect to 1 M 3 S0 6 T1 GND or Vcc or floating (no 1 1 8 connection). 1) Note: CLK output frequency=ICLK 4. Output enable, tri-state CLK OE 7 I 2) Note: M=Leave unconnected (self-biases to output when low. Internal pull-up. Vcc/2). Crystal connection. Leave X2 8 XO unconnected for clock input. 2014-08-0004 PT0138-5 08/14/14 1 PT7C4511 PLL Clock Multiplier Block Diagram OE S0 PLL Clock Synthesis Output and CLK Buffer S1 Control Circuit X1/ICLK Crystal X2 Oscillator V GND CC External Components Decoupling Capacitor pads for small capacitors from X1 to ground and from As with any high-performance mixed-signal IC, the X2 to ground. These capacitors are used to adjust the PT7C4511 must be isolated from system power supply stray capacitance of the board to match the nominally noise to perform optimally. A decoupling capacitor of required crystal load capacitance. Because load 0.01F or 0.1uF must be connected between VCC and capacitance can only be increased in this trimming the GND. It must be connected close to the PT7C4511 process, it is important to keep stray capacitance to a to minimize lead inductance. No external power supply minimum by using very short PCB traces (and no vias) filtering is required for the PT7C4511. between the crystal and device. Crystal capacitors, if Series Termination Resistor needed, must be connected from each of the pins X1 A 33 terminating resistor can be used next to the and X2 to ground. The value (in pF) of these crystal CLK pin for trace lengths over one inch. caps should equal C *2. In this equation, C = crystal L L Crystal Load Capacitors load capacitance in pF. Example: For a crystal with a 15 There is no on-chip capacitance build-in chip. A pF load capacitance, each crystal capacitor would be parallel resonant, fundamental mode crystal should be 30pF. used. The device crystal connections should include Maximum Ratings Note: Stresses greater than those listed under MAXIMUM o o Storage Temperature ..................................................................................... - 65 C to +150 C RATINGS may cause permanent damage to the o o device. This is a stress rating only and functional Ambient Operating Temperature ................................................................... -40 C to +85 C operation of the device at these or any other condi- Supply Voltage to Ground Potential (V ) ................................................... - 0.3V to +7.0V CC tions above those indicated in the operational sec- Inputs(Referenced to GND) ............................................. -0.5V to V +0.5V CC tions of this specification is not implied. Exposure to Clock Output(Referenced to GND) ................................ -0.5V to V +0.5V CC absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Sym Parameter Conditions Min Typ Max Unit V Supply voltage - 3.0 - 5.5 V CC T Operating temperature - -40 - +85 C A 2014-08-0004 PT0138-5 08/14/14 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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