Precision Edge PROGRAMMABLE SY89429A Micrel, Inc. Precision Edge FREQUENCY SYNTHESIZER SY89429A (25MHz to 400MHz) FEATURES n Improved jitter performance over SY89429 n 25MHz to 400MHz differential PECL outputs Precision Edge n 25ps peak-to-peak output jitter DESCRIPTION n Minimal frequency over-shoot n Synthesized architecture The SY89429A is a general purpose, synthesized clock n Serial 3 wire interface source targeting applications that require both serial and n Parallel interface for power-on parallel interfaces. Its internal VCO will operate over a range of frequencies from 400MHz to 800MHz. The differential PECL n Internal quartz reference oscillator driven by quartz output can be configured to be the VCO frequency divided by crystal or PECL source 2, 4, 8 or 16. With the output configured to divide the VCO n PECL output can operate with either +3.3V or +5V frequency by 2, and with a 16MHz external quartz crystal used VCC OUT power supply to provide the reference frequency, the output frequency can n External loop filter optimizes performance/cost be specified in 1MHz steps. n Applications note (AN-06) for ease of design-ins n Available in PLCC and SOIC 28-pin packages PIN CONFIGURATION M 0 1 28 /P LOAD M 1 2 27 VCC1 25 24 23 22 21 20 19 M 2 3 26 XTAL2 S CLOCK 26 18 N 1 S DATA M 3 4 25 XTAL1 27 17 N 0 S LOAD 28 16 M 8 M 4 5 24 LOOP REF PLCC VCC QUIET 1 15 M 7 TOP VIEW M 5 6 23 LOOP FILTER LOOP FILTER M 6 2 14 SOIC M 6 7 22 VCC QUIET LOOP REF 3 13 M 5 TOP VIEW M 7 8 21 S LOAD XTAL1 4 12 M 4 5 6 7 8 9 10 11 M 8 9 20 S DATA N 0 10 19 S CLOCK N 1 11 18 VCC OUT GND (TTL) 12 17 FOUT TEST 13 16 /FOUT VCC (TTL) 14 15 GND APPLICATIONS n Workstations n Advanced communications n High end consumer n High-performance computing n RISC CPU clock n Graphics pixel clock n Test equipment n Other high-performance processor-based applications Precision Edge is a registered trademark of Micrel, Inc. Rev.: K Amendment: /0 1 Issue Date: July 2009 XTAL2 VCC OUT VCC1 FOUT /P LOAD /FOUT M 0 GND M 1 VCC (TTL) M 2 TEST M 3 GND (TTL) Precision Edge SY89429A Micrel, Inc. BLOCK DIAGRAM +5.0V PLL FREF 8 PHASE DETECTOR 10-25MHz VCO Fundamental PECL Crystal OSC M N FOUT or 400 800 PECL MHz Source INTERFACE 3 WIRE SERIAL TEST INTERFACE LOGIC PARALLEL CONFIG. INFO DETAILED BLOCK DIAGRAM +5.0V +5.0V 6, 21 2 3 1 LOOP REF LOOP FILTER VCC QUIET VCC1 FREF PHASE DETECTOR 8 400-800 VCO MHz +5.0V VCC OUT 25 1025MHz T110 4 1 0 Fundamental XTAL1 Crystal 24 or FOUT 9-BIT M N OSC 23 PECL COUNTER (2,4,8,16) 5 FOUT Source XTAL2 L = LATCH H = Transparent FOUT 4 7 LATCH LATCH 6 28 S CLOCK M S LOAD LOW 5 LATCH 20 FOUT 4 7 TEST P LOAD 0 1 0 1 3 M 2 FREF 1 HIGH 27 9-BIT SR S DATA 2-BIT SR 3-BIT SR 0 26 S CLOCK 19,22 8 -> 16 17,18 9 2 M 8:0 N 1:0 NOTE: Pin numbers reference PLCC pinout. 2