GN D VCXO and Synchronous Ethernet 810251I Jitter Attenuator Data Sheet General Description Features The 810251I is a high performance, low jitter/low phase noise One single-ended output (LVCMOS or LVTTL levels), output Impedance: 15 VCXO. The 810251i uses a low frequency and low cost pullable crystal to achieve jitter attenuation for synchronous Ethernet Phase jitter attenuation by the VCXO-PLL using a 25MHz pullable external crystal (XTAL) applications. The 810251I can take an input of either 25MHz or 125MHz and produce a single LVCMOS output of 25MHz. Input frequencies: 25MHz or 125MHz The device is packaged in a small 16 lead TSSOP package and is Output frequency: 25MHz ideal for use on space constrained boards typically encountered in PLL loop bandwidth adjustable by external components most synchronous ethernet applications. 25MHz or 125MHz auto input frequency detect Full 3.3V or 2.5V supply voltage Applications -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Synchronous Ethernet v0.39a End equipment compliant with Std IEEE 802.039a Block Diagram Pin Assignment PLL SEL 1 16 CLK IN (External loop filter inputs.) VDD 2 GND 15 LF1 LF0 14 LF1 Reserved 3 Q 13 LF0 OE 4 VDDO 12 GND 5 25MHz OE 6 11 XTAL IN 7 VDDA 10 XTAL OUT 8 VDD 9 (25MHz or 125MHz input frequency auto detect) 810251I CLK IN Pre- 16-Lead TSSOP PFD CP VCXO 1 divider Q 4.4mm x 5.0mm x 0.925mm 0 (1 or 5) 25MHz package body VCXO-PLL G Package Top View 2016 Integrated Device Technology, Inc 1 Revision B March 3, 2016 XTAL IN XTAL OUT PLL SEL810251I Data Sheet Table 1. Pin Descriptions Number Name Type Description When logic HIGH, the VCXO-PLL is enabled. When LOW, the VCXO-PLL is in 1 PLL SEL Input Pullup bypass mode. LVCMOS/LVTTL interface levels. 2, 9, 12 GND Power Power supply ground. 3 Reserved Reserved Reserved pin. Do not connect. 4 Q Output Single-ended clock output. LVCMOS/ LVTTL interface levels. 5V Power Output power supply pin. DDO 6 OE Input Pullup Output enable pin for Q output. LVCMOS/LVTTL interface levels. 7V Power Analog supply pin. DDA 8, 15 V Power Core supply pins. DD 10, XTAL OUT, Input VCXO crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 11 XTAL IN Analog 13, 14 LF0, LF1 Input/ Loop filter connection node pins. Output 16 CLK IN Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN V V = 3.465V 8 pF DD, DDO C Power Dissipation Capacitance PD V V = 2.625V 5 pF DD, DDO R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.3V5% 15 DDO R Output Impedance OUT V = 2.5V5% 20 DDO 2016 Integrated Device Technology, Inc 2 Revision B March 3, 2016