SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840271I General Description Features The ICS840271I is a PLL-based Frequency Clock frequency translator for Synchronous Ethernet applications ICS Translator intended for use in telecommunication HiPerClockS applications such as Synchronous Ethernet. The One single-ended output (LVCMOS or LVTTL levels), 16 output impedance internal PLL translates Ethernet clock frequencies such as 125MHz (1Gb Ethernet), 156.25MHz Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, (10GbE XAUI) and 161.1328MHz (10Gb Ethernet) to an output LVHSTL, SSTL, HCSL input levels frequency of 25MHz. The PLL does not any require external Supports input clock frequencies of: 125MHz, 156.25MHz or components. The input frequency is selectable by a 2-pin 161.1328MHz interface. The ICS840271I is optimized for low cycle-to-cycle jitter Generates a 25MHz output clock signal on the 25MHz output signal. The input of the device accepts Internal resistor bias on nCLK pin allows the user to drive CLK differential (LVPECL, LVDS, LVHSTL, SSTL, HCSL) or input with external single-ended (LVCMOS/LVTTL) input levels single-ended (LVCMOS) signals. The extended temperature range Internal PLL is optimized for low cycle-to-cycle jitter at the supports telecommunication and networking equipment output requirements. The ICS840271I uses a small RoHS 6, 8-pin Full 3.3V or 2.5V supply voltage TSSOP package and is an effective solution for space-constrained applications. -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram V 1 8 V DDA DD SEL0 2 7 Q CLK Pre- PLL 3 6 GND CLK divider nCLK Q Output 4 5 SEL1 nCLK Feedback divider divider 25 MHz ICS840271I 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm Input Control Logic 00 = PLL Bypass package body SEL(1:0) 01 = 161.1328125 MHz G Package 10 = 156.2500000 MHz 11 = 125.0000000 MHz Top View IDT / ICS SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 1 ICS840271BGI REV. A APRIL 23, 2009ICS840271I SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Table 1. Pin Descriptions Number Name Type Description 1V Power Analog supply pin. DDA Selects the input reference frequency and the PLL bypass mode. 2 SEL0 Input Pulldown LVCMOS/LVTTL interface levels. See Table 3. 3 CLK Input Pulldown Non-inverting differential clock input. Pullup/ 4 nCLK Input Inverting differential clock input. Internal resistor bias to V /2. DD Pulldown Selects the input reference frequency and the PLL bypass mode. 5 SEL1 Input Pullup LVCMOS/LVTTL interface levels. See Table 3. 6 GND Power Power supply ground. 7 Output Single-ended clock output. LVCMOS/LVTTL interface levels. Q 8V Power Core supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 16 DD R Output Impedance OUT V = 2.625V 19 DD Function Tables Table 3. SEL 1:0 Function Table Inputs SEL1 SEL0 CLK, nCLK (MHz) Mode Output (MHz) 0 0 REF PLL Bypass REF/ 5 0 1 161.1328125 PLL Enabled 25 1 (default) 0 (default) 156.25 PLL Enabled 25 1 1 125 PLL Enabled 25 NOTE: REF = Input clock signal frequency IDT / ICS SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 2 ICS840271BGI REV. A APRIL 23, 2009