VDD Crystal-to-HCSL 100MHz ICS841S104I TM PCI Express Clock Synthesizer DATA SHEET General Description Features The ICS841S104I is a PLL-based clock synthesizer specifically Four 0.7V current mode differential HCSL output pairs designed for PCI Express Clock applications. This device Crystal oscillator interface: 25MHz generates a 100MHz differential HCSL clock from an input reference Output frequency: 100MHz of 25MHz. The input reference may be derived from an external RMS phase jitter 100MHz (12kHz 20MHz): 1.145ps (typical) source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the XTAL IN pin with Cycle-to-cycle jitter: 20ps (maximum) the XTAL OUT pin left floating.The device offers spread spectrum 2 I C support with readback capabilities up to 400kHz 2 clock output for reduced EMI applications. An I C bus interface is Spread Spectrum for electromagnetic interference (EMI) reduction used to enable or disable spread spectrum operation as well as 3.3V operating supply mode select either a down spread value of -0.35% or -0.5%.The ICS841S104I is available in a lead-free 24-Lead package. -40C to 85C ambient operating temperature Available lead-free (RoHS 6) package PCI Express Gen 1, 2, 3 jitter compliant HiPerClockS Block Diagram Pin Assignment SRCC4 SRCT3 1 24 25MHz 4 XTAL IN SRCC3 2 23 SRCT4 Divider SRCT 1:4 OSC PLL V SS 3 22 VDD 4 Network SRCC 1:4 XTAL OUT V 4 21 SDATA DD SRCT2 5 20 SCLK SRCC2 6 19 XTAL OUT Pullup SDATA 2 4 SRCT1 7 18 XTAL IN I C Pullup SCLK Logic SRCC1 8 17 V SS 9 16 VSS V nc DD 10 15 IREF V SS 11 14 VDDA 12 13 VSS IREF ICS841S104I 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View ICS841S104EGI REVISION A JUNE 18, 2010 1 2010 Integrated Device Technology, Inc.TM ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS CLOCK SYNTHESIZER Table 1. Pin Descriptions Number Name Type Description 1, 2 SRCT3, SRCC3 Output Differential output pair. HCSL interface levels. 3, 9, 11, 13, 16 V Power Power supply ground. SS 4, 10, 17, 22 V Power Positive supply pins. DD 5, 6 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels. 7, 8 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels. An external fixed precision resistor (475 ) from this pin to ground provides a 12 IREF Input reference current used for differential current-mode SRCCx, SRCTx clock outputs. Power Analog supply for PLL. 14 V DDA 15 nc Unused No connect. 18, XTAL IN, Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 19 XTAL OUT 2 I C compatible SCLK. This pin has an internal pullup resistor. 20 SCLK Input Pullup LVCMOS/LVTTL interface levels. 2 I C compatible SDATA. This pin has an internal pullup resistor. Open drain. 21 SDATA I/O Pullup LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output Differential output pair. HCSL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP ICS841S104EGI REVISION A JUNE 18, 2010 2 2010 Integrated Device Technology, Inc.