XTAL IN Femtoclock Crystal-To-LVHSTL 8422002I-07 Frequency Synthesizer Data Sheet General Description Features The 8422002I-07 is a 2 output LVHSTL Synthesizer optimized to Two LVHSTL outputs (V = 1.2V) OH max generate Fibre Channel reference clock frequencies and is a Selectable crystal oscillator interface or member of the family of high performance clock solutions from LVCMOS/LVTTL single-ended input IDT. Using a 26.5625MHz 18pF parallel resonant crystal, the Supports the following output frequencies: 212.5MHz, following frequencies can be generated based on the 2 frequency 187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz select pins (F SEL 1:0 ): 212.5MHz, 187.5MHz, 159.375MHz, VCO range: 560MHz - 680MHz rd 106.25MHz and 53.125MHz. The 8422002I-07 uses IDTs 3 RMS phase jitter 212.5MHz, using a 25MHz crystal generation low phase noise VCO technology and can achieve 1ps (637kHz - 10MHz): 0.59ps (typical) design target or lower typical rms phase jitter, easily meeting Fibre Channel jitter Power supply modes: requirements. The 8422002I-07 is packaged in a 20-pin TSSOP, Core/Output EPad package. 3.3V/1.8V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Frequency Select Function Table Inputs Input Frequency (MHz) F SEL1 F SEL0 M Div. Value N Div. Value M/N Div. Value Output Frequency (MHz) 26.5625 0 (default) 0 (default) 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 (default) 0 (default) 24 3 8 187.5 Block Diagram Pin Assignment nc 1 20 VDDO 2 Pulldown F SEL 1:0 VDDO 2 19 Q1 Q0 3 18 nQ1 Pulldown nPLL SEL Q0 nQ0 4 17 GND MR 5 16 VDD F SEL 1:0 nQ0 Pulldown nPLL SEL 6 15 nXTAL SEL REF CLK 0 0 3 (default) 11 1 nc 7 14 REF CLK 0 1 4 VDDA 8 13 26.5625MHz 1 0 6 XTAL IN F SEL0 9 12 XTAL OUT Q1 1 1 12 Phase F SEL1 0 VDD 10 11 OSC 0 Detector nQ1 XTAL OUT 422002I-07 Pulldown 20-Lead TSSOP, EPad nXTAL SEL 4.4mm x 6.5mm x 0.90mm package body M = 24 (fixed) G Package Top View Pulldown MR 2016 Integrated Device Technology, Inc 1 Revision A January 29, 20168422002I-07 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 7 nc Unused No connect. 2, 20 V Power Output supply pins. DDO 3, 4 Q0, nQ0 Output Differential output pair. LVHSTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx 5 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL select control. When LOW, the selected reference clock is frequency-multiplied by the PLL. When HIGH, the PLL is bypassed and the 6 nPLL SEL Input Pulldown selected reference clock is routed directly to the output dividers. LVCMOS/LVTTL interface levels. 8V Power Analog supply pin. DDA F SEL0, 9, 11 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. F SEL1 10, 16 V Power Core supply pins. DD XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, 12, 13 Input XTAL IN XTAL IN is the input. 14 REF CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF CLK inputs as the PLL Reference source. 15 nXTAL SEL Input Pulldown Selects XTAL inputs when LOW. Selects REF CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. 18, 19 nQ1, Q1 Output Differential output pair. LVHSTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision A January 29, 2016