FemtoClock Crystal-to-LVDS Frequency ICS844246DI Synthesizer w/Integrated Fanout Buffer DATA SHEET General Description Features The ICS844246DI is a Crystal-to-LVDS Clock Synthesizer/Fanout Six LVDS output pairs Buffer designed for Fibre Channel frequencies and Gigabit Ethernet Crystal oscillator interface applications. The output frequency can be set using the frequency Output frequency range: 53.125MHz to 333.3333MHz select pins and a 25MHz crystal for Ethernet frequencies, or a Crystal input frequency range: 25MHz to 33.333MHz 26.5625MHz crystal for a Fibre Channel. The low phase noise characteristics of the ICS844246DI make it an ideal clock for these RMS phase jitter 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.416ps (typical) demanding applications. Full 3.3V or mixed 3.3V core, 2.5V output supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Select Function Table Inputs Function FB SEL N SEL1 N SEL0 M Divide N Divide M/N 000 20 2 10 001 20 4 5 010 20 5 4 0 1 1 20 8 2.5 (default) 100 24 3 8 101 24 4 6 110 24 6 4 1 1 1 24 12 2 Block Diagram Pin Assignment Q0 VDDO 1 24 Q3 VDDO 2 23 nQ3 nQ0 nQ2 3 22 Q4 Pullup PLL BYPASS Q2 4 21 nQ4 Q1 nQ1 5 20 Q5 Q1 6 19 nQ5 1 nQ1 N nQ0 7 18 N SEL1 Q0 8 17 GND XTAL IN Output OSC PLL Q2 PLL BYPASS 9 16 GND 0 Divider VDDA 10 15 N SEL0 XTAL OUT nQ2 VDD 11 14 XTAL OUT FB SEL 12 13 XTAL IN Q3 M ICS844246DI Feedback nQ3 24-Lead TSSOP, E-Pad Divider 4.4mm x 7.8mm x 0.925mm Q4 package body nQ4 Pulldown G Package FB SEL Top View Pullup N SEL0 Q5 Pullup N SEL1 nQ5 ICS844246DGI REVISION A NOVEMBER 28, 2012 1 2012 Integrated Device Technology, Inc. ICS844246DI Data Sheet FEMTOCLOCK CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 V Power Output supply pins. DDO 3, 4 nQ2, Q2 Output Differential output pair. LVDS interface levels. 5, 6 nQ1, Q1 Output Differential output pair. LVDS interface levels. 7, 8 nQ0, Q0 Output Differential output pair. LVDS interface levels. Selects between the PLL and crystal inputs as the input to the dividers. 9 PLL BYPASS Input Pullup When LOW, selects PLL. When HIGH, bypasses the PLL. LVCMOS / LVTTL interface levels. 10 V Power Analog supply pin. DDA 11 V Power Core supply pin. DD 12 FB SEL Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. 13 XTAL IN, Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. Input 14 XTAL OUT N SEL0, Output frequency select pin. LVCMOS/LVTTL interface levels. 15, 18 Input Pullup N SEL1 16, 17 GND Power Power supply ground. 19, 20 nQ5, Q5 Output Differential output pair. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS844246DGI REVISION A NOVEMBER 28, 2012 2 2012 Integrated Device Technology, Inc.