8-Channel Universal Frequency 8A34041 Datasheet Translator 8 differential / 16 single-ended clock inputs Overview Support frequencies from 1kHz to 1GHz The 8A34041 8-Channel Universal Frequency Translator is a Any input can be mapped to any or all of the timing channels highly integrated timing device that generates synchronous or Redundant inputs frequency independent of each other asynchronous clocks from its reference inputs. The device is usable in any synthesizer or jitter attenuator application, including Any input can be designated as external frame/sync pulse of Optical Transport Network (OTN) and Synchronous Ethernet PPES (pulse per even second), 1 PPS (Pulse per Second), (SyncE) systems. 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz associated with a selectable reference clock input Typical Applications Per-input programmable phase offset of up to 1.638 s in 50ps steps Core and access IP switches / routers Reference monitors qualify/disqualify references depending on Synchronous Ethernet equipment LOS, activity, frequency monitoring, and/or LOS input pins 10Gb, 40Gb, and 100Gb Ethernet interfaces Loss of Signal (LOS) input pins (via GPIOs) can be assigned Wireless infrastructure for 4.5G and 5G network equipment to any input clock reference OTN Muxponders and line cards Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive, and other Features programmable settings Close-in phase noise complies with Common Public Radio System APLL operates from fundamental-mode crystal: 25MHz Interface (CPRI) frequency synchronization requirements to 54MHz or from a crystal oscillator Supports all ITU-T G.709 frequencies System DPLL accepts an XO, TCXO, or OCXO operating at Meets OTN jitter and wander requirements per ITU-T G.8251 virtually any frequency from 1MHz to 150MHz Eight independent timing channels DPLLs can be configured as DCOs to synthesize clocks under Each can act as a frequency synthesizer, jitter attenuator, the control of an external algorithm Digitally Controlled Oscillator (DCO), or Digital Phase Lock DCOs generate PTP based clocks with frequency resolution -16 Loop (DPLL) less than 1.11 10 DPLL Digital Loop Filters (DLFs) are programmable with cut 2 Supports 1MHz I C or 50MHz SPI serial processor ports off frequencies from 1.1Hz to 22kHz The device can configure itself automatically after reset via: Generates output frequencies that are independent of input Internal customer definable One-Time Programmable frequencies via a Fractional Output Divider (FOD) memory with up to 16 different configurations Each FOD supports output phase tuning with 50ps 2 2 Standard external I C EPROM via separate I C Master Port resolution 1149.1 JTAG Boundary Scan 12 Differential / 24 LVCMOS outputs 10 10 mm with 0.8mm ball pitch, 144-CABGA package Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) Jitter below 150fs RMS (10kHz to 20MHz) LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL output modes supported Differential output swing is selectable: 400mV / 650mV / 800mV / 910mV Independent output voltages of 3.3V, 2.5V, or 1.8V LVCMOS additionally supports 1.5V or 1.2V The clock phase of each output is individually programmable in 1ns to 2ns steps with a total range of 180 2021 Renesas Electronics Corporation 1 December 14, 20218A34041 Datasheet 1 Block Diagram Figure 1. Block Diagram XO DPLL (Optional) OSCI OSCO To FODs System Osc FOD DPLL System Combo Bus APLL (Frequency Data) Div Out Q0 DPLL / FOD DCO 0 Div Out Q1 CLK0 Div Out Q2 DPLL / FOD DCO 1 Div Out Q3 CLK1 Div Out Q4 DPLL / FOD DCO 2 CLK2 Div Out Q5 Reference Div Out Q6 Monitors DPLL / CLK3 FOD DCO 3 Div Out Q7 Reference Switching CLK4 DPLL / State FOD Div Out Q8 DCO 4 Machines CLK5 DPLL / FOD Div Out Q9 DCO 5 CLK6 DPLL / FOD Div Out Q10 DCO 6 CLK7 DPLL / FOD Div Out Q11 DCO 7 Status and Configuration OTP Registers 2 2 2 I C Master SPI/I C 0 SPI/I C 1 GPIO / JTAG Description The 8A34041 8-Channel Universal Frequency Translator is a highly integrated timing device that generates synchronous or asynchronous clocks from any of its reference inputs. This is usable in any synthesizer or jitter attenuator application, including Optical Transport Network (OTN) and Synchronous Ethernet (SyncE) systems. The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal connected between the OSCI and OSCO pins. 1 This product is covered by one or more of the following patents: US 9,369,270, US 10,355,699, US 10,075,284, US 9,628,255, and US 9,479,182. 2021 Renesas Electronics Corporation 2 December 14, 2021